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• Intel® MAX 10 Commercial [10M08SAU169C8G]

  • Package: UBGA-169

  • Speed Grade: C8 (Slowest)

  • Temperature: 0°C ~ to 85°C

  • Package compatible device 10M0210M08...10M16 as assembly variant on request possible

• SDRAM Memory up to 64Mb, 166MHzDual High Speed USB to 32 Mbyte (8Mbyte default)

• USB 2.0 Multipurpose UART/FIFO IC

• 64Mb Quad SPI Flash

• 4Kb EEPROM Memory 

• (FT2232H)

  • 4 Kbit EEPROM Memory for FTDI configuration data
  • Micro USB Receptacle (communication and power)

• SPI Flash - NOT INSTALLED (only special option)

• 8x User LED 

• Micro USB2 Receptacle 90USB Connector

• 16 Bit 500 kSPS Analog to Digital Converter with 1 MSPS or 500 kSPS

• 2x SMA Female Connector

• I/O interface: 23x GPIO

• Power Supply:

• 5V

Minimum 1A

5V (from USB)

• Dimension:

  25m

  25 mm x 86.

  5m

  5 mm

• Others:

  • Instrumentation Amplifier

  • Differential Amplifier

  • Operational Amplifier

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1. SMA Connector, J5...6
2. Amplifier, U12
3. Analog to Digital ConvertorConverter, U6
4. Voltage Reference, U8
5. Voltage Regulator, U10 - U13 - U16
6. Switching Voltage3 Voltage Regulator/LDO, U11 - U4
7. SDRAM Memory, U2
8. Intel® MAX 10 FPGA, U1
9. SPI Flash Memory, U5 (not populated)
10. 12.00 MHz MEMS oscillator, U7
11. FTDI USB2 USB to JTAG/UART adapter/FIFO, U3
12. User LEDs, D2...9
13. 4Kb EEPROM, U9
14. Configuration LED (Red) , D10
15. Power-on LED (Green), D1
16. Push button, S1...2
17. Micro USB2 ReceptacleUSB Connector, J9
18. 1x14 pin header , J2 (Not assembled), J2
19. 1x6 pin header , J4 (Not assembled), J4
20. Jumper, J3
21. 1x14 pin header , J1 (Not assembled), J1

Initial Delivery State

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Configuration Signals

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (SPI Flash U5) or (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.

Reset process must be done FPGA Reconfigration can be triggered by pressing push button S1.

Signals, Interfaces and Pins

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Micro-

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USB Connector

The Micro-USB2 connector J9 provides an interface to access the UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PC.

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On-board Peripherals

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SDRAM

TEI0016 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

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FTDI FT2232H

The FTDI chip U3 converts signals from USB2 USB to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity features of the FT2232H chip.
FTDI FT2232H chip channel A is used in MPPSE mode for JTAG, 6 I/O's of . Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfacesis configured to be used as in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

SPI Flash

On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.

SPI Flash

Optional SPI flash device maybe assembled in custom variants, normally it is not populated.

EEPROM

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.in the EEPROM U9.

ADC

The boards with article nuber - TEI0016-03-08-C8A - are equipped with the Analog DevicesADC - ADAQ7988BCCZ - 16-bit 500kSPS,
boards wit article number TEI0016-03-08-C8B are equipped with the Analog Devices ADC - ADAQ7980BCCZ - 16-bit 1MSPS.

The ADC can be distinguished via its part code:

• TEI0016-03-08-C8A: ADAQ7988BCCZ - 16-bit 500kSPS - starts with Y6H
• TEI0016-03-08-C8B: ADAQ7980BCCZ - 16-bit 1.0MSPS - starts with Y6F

EECS

ADC

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Push Buttons

Clock Sources

Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

• Power on-sequence
• Power distribution
• Voltage monitoring circuit

Power and Power-On Sequence

Power Supply

The module is supplied from USB (optionally via unpopulated pin header).

Power Consumption

Power Supply

To power-up the module, power supply with minimum current capability of 1A is recommended.

Power Consumption

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* TBD - To Be Determined

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Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed. After power on the Green LED (D1) must be on.

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* TBD - To Be Determined

Power Distribution Dependencies

Voltage

J9

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Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed. After power on, the green LED (D1) will be on.

Power Rails