Page History

Page properties

hidden	true
id	Comments

Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"

Date	Version	Changes	Author
2023-12-14	3.1.17	updated according to Vivado 2023.2	ma
2023-06-13	3.1.16	Design flow: added alternative programming files in Petalinux added chapter FSBL Patch in Software Design - Petalinux	ma
2023-06-01	3.1.15	removed u-boot.dtb from Design flow	ma
2023-06-01	3.1.14	expandable lists for revision history and supported hardware	wh
2023-05-25	3.1.13	updated according to Vivado 2022.2	ma
2023-02-08	3.1.12	removed content of Special FSBL for QSPI programming	ma
2022-08-24	3.1.11	Modification from link "available short link"	ma
2022-01-25	3.1.10	removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin corrected Boot Source File in Boot Script-File	ma
2022-01-14	3.1.9	extended notes for microblaze boot process with linux add u.boot.dtb to petalinux notes add dtb to prebuilt content replace 20.2 with 21.2	jh
2021-06-28	3.1.8	added boot process for Microblaze minor typos, formatting	ma
2021-06-01	3.1.7	carrier reference note	jh
2021-05-04	3.1.6	removed zynq_ from zynq_fsbl	ma
2021-04-28	3.1.5	added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export minor typos, formatting	ma
2021-04-27	3.1.4	Version History changed from list to table Design flow removed step 5 from Design flow changed link from TE Board Part Files to Vivado Board Part Flow changed cmd shell from picture to codeblock added hidden template for "Copy PetaLinux build image files", depending from hardware added hidden template for "Power on PCB", depending from hardware Usage update of boot process Requirements - Hardware added "^*used as reference" for hardware requirements all placed a horizontal separation line under each chapter heading changed title-alignment for tables from left to center all tables added "<project folder>\board_files" in Vivado design sources	ma
	3.1.3	Design Flow formatting Launch formatting	ma
	3.1.2	minor typing corrections replaced SDK by Vitis changed from / to \ for windows paths replaced <design name> by <project folder> added "" for path names added boot.scr description added USB for programming	ma
	3.1.1	swapped order from prebuilt files minor typing corrections removed Win OS path length from Design flow, added as caution in Design flow	ma
	3.1	Fix problem with pdf export and side scroll bar update 19.2 to 20.2 add prebuilt content option
	3.0	add fix table of content add table size as macro removed page initial creator

Custom_table_size_100

Page properties

hidden	true
id	Comments

Important General Note:

Export PDF to download, if vivado revision is changed!

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template (note: inner scroll ignore/only only with drawIO object):

Scroll Title

anchor	Figure_xyz
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, use

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)
Scroll Title
anchor Table_xyz
title Text
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default
style
widths
sortByColumn 1
sortEnabled false
cellHighlighting true
Example Comment
1 2

...

Overview

Scroll Ignore

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

Page properties

hidden	true
id	Comments

Notes :

short description of the design
Short Link of "Scroll only" macro:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info
- List of available short links: https://wiki.trenz-electronic.de/display/TI/Redirects

Linux with basic periphery of TE0808 StarterKit (TEBF0808 Carrier).

Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

Key Features

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id	Comments

Notes :

Add basic key futures, which can be tested with the design

Excerpt
Vitis/Vivado 20212023.2.1 TEBF0808 Linux USB ETH MAC from EEPROM PCIe SATA SD I2C RGPIO Display Port (DP) user LED access Modified FSBL for Si5345 programming / petalinux patch

Revision History

Page properties

hidden	true
id	Comments

Notes :

add every update file on the download
add design changes on description

Expand

title	Expand List

Scroll Title

anchor	Table_DRH
title-alignment	center
title	Design Revision History

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Date	Vivado	Project Built	Authors	Description

2023

2024-

04

11-

13

12

2021

2023.2

.1

TE0808-StarterKit-vivado_

2021

2023.2-build_

20

4_

20230413092755

20241112124835.zip
TE0808-StarterKit_noprebuilt-vivado_

2021

2023.2-build_

20

4_

20230413092755

20241112124835.zip

Manuela Strücker

new assembly variants

bugfix QSPI partition for image.ub in Linux
update device tree

2024-05

2022-09

-29

2021

2023.2

.1

TE0808-StarterKit-vivado_

2021

2023.2-build_

17

4_

20220929082218

20240528104904.zip
TE0808-StarterKit_noprebuilt-vivado_

2021

2023.2-build_

17

4_

20220929082218

20240528104904.zip

Manuela Strücker

script update

new assembly variants

2022-09-12

update petalinux bugfix board files for eMMC
2024-03-13	2023.2

2021.2.1

TE0808-StarterKit-vivado_

2021

2023.2-build_

15

4_

20220912090625

20240313131239.zip
TE0808-StarterKit_noprebuilt-vivado_

2021

2023.2-build_

15

4_

20220912090625

20240313131239.zip

Manuela Strücker

update board part files compatible to Vivado 2021.2.1

2023.2 release new assembly variants
2023-06-01	2022

2022-03-162021

.2	TE0808-StarterKit-vivado_

2021

2022.2-build_

11

1_

20220316082848

20230601094128.zip
TE0808-StarterKit_noprebuilt-vivado_

2021

2022.2-build_

11

1_

20220316082848

20230601094128.zip

Manuela Strücker

2021

2022.2 release

update board files

2021-05-12

new assembly variants
2023-04-13	2021.2.1

2020.2

TE0808-StarterKit-vivado_

2020

2021.2-build_

5

20_

20210512133800

20230413092755.zip
TE0808-StarterKit_noprebuilt-vivado_

2020

2021.2-build_

5

20_

20210512133822

20230413092755.zip

John Hartfiel

update board files
boot.scr update to version1 → image.ub on sd, eMMC, USB possible

Manuela Strücker	new assembly variants
2022-09-29	2021.2.1

2021-02-052020.2

TE0808-StarterKit-vivado_

2020

2021.2-build_

1

17_

20210205120058

20220929082218.zip
TE0808-StarterKit_noprebuilt-vivado_

2020

2021.2-build_

1

17_

20210205120122

20220929082218.zip

John Hartfiel

bugfix init.sh script usage

2021-02-05

Manuela Strücker	script update new assembly variants
2022-09-12	2021.2.1

2020.2

TE0808-StarterKit

_noprebuilt

-vivado_

2020

2021.2-build_

1

15_

20210204142828

20220912090625.zip
TE0808-StarterKit_noprebuilt-vivado_

2020

2021.2-build_

1

15_

20210204142713

20220912090625.zip

John Hartfiel

2020.2 update
add boot.scr file
device tree has change
petalinux fsbl patch (betaversion)

Manuela Strücker	update board part files compatible to Vivado 2021.2.1
2022-03-16	2021

2020-09-292019

.2	TE0808-StarterKit

_noprebuilt

-vivado_

2019

2021.2-build_

15

11_

20200928195324

20220316082848.zip
TE0808-StarterKit_noprebuilt-vivado_

2019

2021.2-build_

15

11_

20200928195304

20220316082848.zip

John Hartfiel

bugfix 8GB board part files

	Manuela Strücker	2021.2 release update board files
2021-05-12	2020

2020-09-222019

.2	TE0808-StarterKit

_noprebuilt

-vivado_

2019

2020.2-build_

14

5_

20200922071643

20210512133800.zip
TE0808-StarterKit_noprebuilt-vivado_

2019

2020.2-build_

14

5_

20200922071704

20210512133822.zip

John Hartfiel

new assembly variants

update board files boot.scr update to version1 → image.ub on sd, eMMC, USB possible
2021-02-05	2020

2020-03-252019

.2	TE0808-StarterKit

_noprebuilt

-vivado_

2019

2020.2-build_

8

1_

20200325083508

20210205120058.zip
TE0808-StarterKit_noprebuilt-vivado_

2019

2020.2-build_

8

1_

20200325083436

20210205120122.zip

John Hartfiel

bugfix init.sh script

update

usage

2020

2021-

01

02-

22

05

2019

2020.2

TE0808-StarterKit_noprebuilt-vivado_

2019

2020.2-build_

3

1_

20200122142340

20210204142828.zip
TE0808-StarterKit-vivado_

2019

2020.2-build_

3

1_

20200122142318

20210204142713.zip

John Hartfiel

2019

2020.2 update

Vitis support

FSBL SI programming procedure update

petalinux device tree and u-boot update

add boot.scr file device tree has change petalinux fsbl patch (betaversion)
2020-09-29	2019.2

2019-08-092018.3

TE0808-StarterKit_noprebuilt-vivado_

2018

2019.

3

2-build_

07

15_

20190809131638

20200928195324.zip
TE0808-StarterKit-vivado_

2018

2019.

3

2-build_

07

15_

20190809131620

20200928195304.zip

John Hartfiel

new assembly variants
small fsbl update(supports all GTR disabled now)

2019-05-07

bugfix 8GB board part files
2020-09-22	2019.2

2018.3

TE0808-StarterKit_noprebuilt-vivado_

2018

2019.

3

2-build_

05

14_

20190507124429

20200922071643.zip
TE0808-StarterKit-vivado_

2018

2019.

3

2-build_

05

14_

20190507124418

20200922071704.zip

John Hartfiel

new assembly

variant

TE Script update

rework of the FSBLs

some additional Linux features

MAC from EEPROM

new assembly variants

remove special compiler flags, which was needed in 2018.2

variants
2020-03-25	2019

2018-07-112018

.2	TE0808-StarterKit_noprebuilt-vivado_

2018

2019.2-build_

02

8_

20180711091558

20200325083508.zip
TE0808-StarterKit-vivado_

2018

2019.2-build_

02

8_

20180711091049

20200325083436.zip

John Hartfiel

small petalinux changes
IO renaming
PL Design changes
additional notes for FSBL generated with Win SDK
changed *.bif

script update
2020-01-22	2019.2

2018-05-242017.4

TE0808-StarterKit_noprebuilt-vivado_

2017

2019.

4

2-build_

10

3_

20180524091231

20200122142340.zip
TE0808-StarterKit-vivado_

2017

2019.

4

2-build_

10

3_

20180524091208

20200122142318.zip

John Hartfiel

solved Linux flash issue

2019.2 update Vitis support FSBL SI programming procedure update petalinux device tree and u-boot update
2019-08-09	2018.3	TE0808-StarterKit

2018-03-292017.4TE0808-StarterKit

_noprebuilt-vivado_

2017

2018.

4

3-build_07_

20180329145308

20190809131638.zip
TE0808-StarterKit-vivado_

2017

2018.

4

3-build_07_

20180329145246

20190809131620.zip

John Hartfiel

new assembly

variant2018-02-06

variants small fsbl update(supports all GTR disabled now)
2019-05-07	2018.3

2017.4

TE0808-StarterKit_noprebuilt-vivado_

2017

2018.

4

3-build_05_

20180206082740

20190507124429.zip
TE0808-StarterKit-vivado_

2017

2018.

4

3-build_05_

20180206082722

20190507124418.zip

John Hartfiel

new assembly variant
TE Script update
rework of the FSBLs
some additional Linux features
MAC from EEPROM
new assembly variants
remove special compiler flags, which was needed in 2018.2

same clk for both VIO

2018-

02

07-

05

11

2017

2018.

4

2	TE0808-StarterKit_noprebuilt-vivado_

2017

2018.

4

2-build_

05

02_

20180205083231

20180711091558.zip
TE0808-StarterKit-vivado_

2017

2018.

4

2-build_

05

02_

20180205083208

20180711091049.zip

John Hartfiel

solved JTAG/Linux problem

small petalinux changes
IO renaming
PL Design changes
additional notes for FSBL generated with Win SDK
changed *.bif

2018-05-24

2018-01-17

2017.4

TE0808-StarterKit_noprebuilt-vivado_2017.4-build_

05

10_

20180117094213

20180524091231.zip
TE0808-StarterKit

_noprebuilt

-vivado_2017.4-build_

05

10_

20180117094231

small board part update

20180524091208.zip

John Hartfiel

solved

USB problem

Linux flash issue

2018-

01

03-

15

29

2017.4

TE0808-StarterKit_noprebuilt-vivado_2017.4-build_

03

07_

20180115092306

20180329145308.zip
TE0808-StarterKit

_noprebuilt

-vivado_2017.4-build_

03

07_

20180115092511

20180329145246.zip

John Hartfiel

rework board part files
rework design

new assembly variant

2018-02-06

2017-12-18

2017.

2

4	TE0808-StarterKit_noprebuilt-vivado_2017.

2

4-build_

07

05_

20171219151749

20180206082740.zip
TE0808-StarterKit-vivado_2017.

2

4-build_

07

05_

20171219151728

20180206082722.zip

John Hartfiel

initial release

Release Notes and Know Issues

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hidden	true
id	Comments

Notes :

add known Design issues and general notes for the current revision
do not delete known issue, add fixed version time stamp if issue fixed

Scroll Title

anchor	Table_KI
title-alignment	center
title	Known Issues

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueIssuesDescriptionWorkaround/SolutionTo be fixed versionXilinx SoftwareIncompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Requestuse corresponding board files for the Vivado versions--MAC from EEPROM

The MAC address stored in the EEPROM is not read out and initialised correctly during start-up.
This is caused by two I2C expanders each switched to the same EEPROM with the same address
i2cswitch@73 --> i2c@5 --> reg = <0x50> and
i2cswitch@77 --> i2c@4 --> reg = <0x50>

Switching the second I2C expander (i2cswitch@77) to another channel in the fsbl solves the error during the start-up procedure.

Solved
with 20220316 update

QSPI FlashFlash programming is not supported with boot mode QSPI or SD.
If flash programming fails, configure device for JTAG boot mode and try again or use oder Vivado Versions for programming. (Vivado 2020.2 or 2019.2)
--Flash access on LinuxDevice tree is not correct on Linuxadd compatibility to "compatible “jedec,spi-nor”"Solved with 20180524 updateUSB UART Terminal is blocked/ SDK Debugging is blockedThis happens only with 2017.4 Linux, when JTAG connection is established on Vivado HW Manager.

Do not use HW Manager connection, or if debugging is necessary:

Boot linux with usb terminal
From the terminal: root root mount ifconfig eth0
Open two new SSH terminals via ethernet: root root , run user application ...
Exit and close the usb terminal

Solved with 20180205 update

same clk for both VIO
2018-02-05	2017.4	TE0808-StarterKit_noprebuilt-vivado_2017.4-build_05_20180205083231.zip TE0808-StarterKit-vivado_2017.4-build_05_20180205083208.zip	John Hartfiel	solved JTAG/Linux problem
2018-01-17	2017.4	TE0808-StarterKit-vivado_2017.4-build_05_20180117094213.zip TE0808-StarterKit_noprebuilt-vivado_2017.4-build_05_20180117094231.zip	John Hartfiel	solved USB problem small board part update
2018-01-15	2017.4	TE0808-StarterKit-vivado_2017.4-build_03_20180115092306.zip TE0808-StarterKit_noprebuilt-vivado_2017.4-build_03_20180115092511.zip	John Hartfiel	rework board part files rework design
2017-12-18	2017.2	TE0808-StarterKit_noprebuilt-vivado_2017.2-build_07_20171219151749.zip TE0808-StarterKit-vivado_2017.2-build_07_20171219151728.zip	John Hartfiel	initial release

Release Notes and Know Issues

Page properties

hidden	true
id	Comments

Notes :

add known Design issues and general notes for the current revision
do not delete known issue, add fixed version time stamp if issue fixed

Scroll Title

anchor	Table_KI
title-alignment	center
title	Known Issues

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Issues	Description	Workaround/Solution	To be fixed version
QSPI Flash	Partition mtd1 is to small for image.ub	change config parameter for QSPI and boot.scr offset	Solved with 202411 update
Xilinx Software	Bugfix ZynqMP with eMMC	changed SD0__PERIPHERAL__IO" value="MIO 13 .. 22" added SD0__DATA_TRANSFER_MODE" value="8Bit"	Solved with 20240528 update
Xilinx Software	Incompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Request	use corresponding board files for the Vivado versions	--
MAC from EEPROM	The MAC address stored in the EEPROM is not read out and initialised correctly during start-up. This is caused by two I2C expanders each switched to the same EEPROM with the same address i2cswitch@73 --> i2c@5 --> reg = <0x50> and i2cswitch@77 --> i2c@4 --> reg = <0x50>	Switching the second I2C expander (i2cswitch@77) to another channel in the fsbl solves the error during the start-up procedure.	Solved with 20220316 update
QSPI Flash	Flash programming is not supported with boot mode QSPI or SD.	If flash programming fails, configure device for JTAG boot mode and try again or use oder Vivado Versions for programming. (Vivado 2020.2 or 2019.2)	--
Flash access on Linux	Device tree is not correct on Linux	add compatibility to "compatible “jedec,spi-nor”"	Solved with 20180524 update
USB UART Terminal is blocked/ SDK Debugging is blocked	This happens only with 2017.4 Linux, when JTAG connection is established on Vivado HW Manager.	Do not use HW Manager connection, or if debugging is necessary: Boot linux with usb terminal From the terminal: root root mount ifconfig eth0 Open two new SSH terminals via ethernet: root root , run user application ... Exit and close the usb terminal	Solved with 20180205 update

Requirements

Software

Page properties

hidden	true
id	Comments

Notes :

list of software which was used to generate the design

Scroll Title

anchor	Table_SW
title-alignment	center
title	Software

Requirements

Software

Page properties

hidden	true
id	Comments

Notes :

list of software which was used to generate the design

Scroll Title

anchor	Table_SW
title-alignment	center
title	Software

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueSoftwareVersionNoteVitis2021.2.1needed, Vivado is included into Vitis installationPetaLinux2021.2neededSI ClockBuilder Pro---optional

Hardware

Page properties

hidden	true
id	Comments

Notes :

list of hardware which was used to generate the design
mark the module and carrier board, which was used tested with an ^*

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Scroll Title

anchor	Table_HWM
title-alignment	center
title	Hardware Modules

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Software	Version	Note
Vitis	2023.2	needed, Vivado is included into Vitis installation
PetaLinux	2023.2	needed
SI ClockBuilder Pro	---	optional

Hardware

Page properties

hidden	true
id	Comments

Notes :

list of hardware which was used to generate the design
mark the module and carrier board, which was used tested with an ^*

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

4GB

Expand

title	Expand List

Scroll Title

anchor	Table_HWM
title-alignment	center
title	Hardware Modules

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Module Model	Board Part Short Name	PCB Revision Support	DDR	QSPI Flash	EMMC	Others	Notes
~~TE0808-ES1~~	es1_2gb	REV03\|REV02	2GB

Module Model

Board Part Short Name

PCB Revision Support

DDR

QSPI Flash

EMMC

Others

Notes

~~TE0808-ES1~~

es1_2gb

REV03|REV02

2GB

64MB

NA

Not longer supported by vivado

~~TE0808-ES2~~

es2_2gb

REV04|REV03

2GB

64MB

NA

Not longer supported by vivado

~~TE0808-2ES2~~

2es2_2gb

REV04|REV03

2GB

64MB

NA

Not longer supported by vivado

TE0808-04-09EG-1EA

9eg_1e_2gb

REV04

2GB

64MB

NA

TE0808-04-09EG-1EB

9eg_1e_4gb

REV04

4GB

64MB

NA

TE0808-04-09EG-1ED

9eg_1e_4gb

REV04

4GB

64MB

NA

1 mm connectors

NA

TE0808-04-09EG-2IB

9eg_2i_4gb

REV04

64MB

NA

Not longer supported by vivado

~~TE0808-~~

04-15EG-1EB 15eg_1e_4gb REV04

~~ES2~~

es2_2gb

REV04|REV03

2GB

4GB

64MB

NA

Not longer supported by vivado

~~TE0808-~~

04-09EG-1EE 9eg_1e_4gb REV04 4GB 128MB

~~2ES2~~

2es2_2gb

REV04|REV03

2GB

64MB

NA

Not longer supported by vivado

TE0808-04-

09EG

06EG-

1EL

1E3

9eg

6eg_1e_

4gb

REV04

4GB

128MB

NA

NA	1 mm connectors

NA

TE0808-04-

09EG

06EG-

2IE^*

1EE

9eg

6eg_

2i

1e_

4gb

REV04

4GB

128MB

NA

TE0808-04-

15EG

09EG-

1EE

1EA

15eg

9eg_1e_

4gb

2gb

REV04

4GB

2GB

128MB

64MB

NA

TE0808-04-

06EG

09EG-

1EE

1EB

6eg

9eg_1e_

4gb

REV04

4GB

128MB

64MB

NA

TE0808-04-

06EG

09EG-

1E3

1ED

6eg

9eg_1e_

4gb

REV04

4GB

128MB

64MB

NA

NA	1 mm connectors

NA

TE0808-04-

6GI21

09EG-

L

1EE

6eg

9eg_

2i

1e_

4gb

REV04

4GB

128MB

NA

1 mm connectors

NA

TE0808-04-

6BI21

09EG-

A

1EL

6eg

9eg_

1i

1e_

4gb

REV04

4GB

128MB

NA

1 mm connectors

NA

TE0808-04-

9GI21

09EG-

A

2IB

9eg_2i_

4gb

REV04

4GB

128MB

64MB

NA

TE0808-04-

9BE21

09EG-

A

2IE

9eg_

1e

2i_

4gb

REV04

4GB

128MB

NA

TE0808-04-6BE21-

L

A

6eg_1e_

4gb

REV04

4GB

128MB

NA

1 mm connectors

NA

TE0808-04-6BE21-

A

L

6eg_1e_

4gb

REV04

4GB

128MB NA NA NA TE0808-04-9BE21-L 9eg_1e_4gb REV04 4GB 128MB NA

128MB

NA

1 mm connectors

NA

TE0808-04-

BBE21

6BI21-

A

15eg

6eg_

1e

1i_

4gb

REV04

4GB

128MB

NA

TE0808-04-6BI21-

X

6eg_1i_

4gb

REV04

4GB

128MB

NA

NA	U41 replaced with schottky

diodes

TE0808-

05

04-

6BE21

6GI21-

L

6eg_

1e

2i_

4gb

REV05

REV04

4GB

128MB

NA

NA	1 mm connectors

NA

TE0808-

05

04-

6BE21

9BE21-

A

6eg

9eg_1e_

4gb

REV05

REV04

4GB

128MB

NA

TE0808-

05

04-

6BI21

9BE21-

D

L

6eg

9eg_

1i

1e_

4gb

REV05

REV04

4GB

128MB

NA

NA	1 mm connectors

SoC without encryption

NA

TE0808-

05

04-

6BI21

9GI21-

X

A

6eg

9eg_

1i

2i_

4gb

REV05

REV04

4GB

128MB

NA

U41 replaced with schottky diodes

TE0808-

05

04-

6BI41

15EG-

X

1EB

6eg

15eg_

1i

1e_

8gb

4gb

REV05

REV04

8GB

4GB

128MB

64MB

NA

U41 replaced with schottky diodes

TE0808-

05

04-

9BE21

15EG-

A

1EE

9eg

15eg_1e_

4gb

REV05

REV04

4GB

128MB

NA

TE0808-

05

04-

9BE21

BBE21-

L

A

9eg

15eg_1e_

4gb

REV05

REV04

4GB

128MB

NA

1 mm connectors

NA

TE0808-05-

9BI41

6BE21-

X

A

9eg

6eg_

1i

1e_

8gb

4gb

REV05

8GB

4GB

128MB

NA

U41 replaced with schottky diodes

TE0808-05-

9GI21

6BE21-

A

F

9eg

6eg_

2i

1e_

4gb

REV05

4GB

128MB

NA

TE0808-05-

9GI21

6BE21-

C

AK

9eg

6eg_

2i

1e_

4gb

REV05

4GB

128MB

NA

SoC without encryption

NA

TE0808-05-

BBE21

6BE21-

A

L

15eg

6eg_1e_

4gb

REV05

4GB

128MB

NA

1 mm connectors

NA

TE0808-05-

BBE21

6BI21-

L

D

15eg

6eg_

1e

1i_

4gb

REV05

4GB

128MB

NA

NA	1 mm connectors

NA

SoC without encryption

TE0808-05-

S002

6BI21-X

15eg

6eg_

1e

1i_4gb

REV05

4GB

128MB

NA

CAO

U41 replaced with schottky diodes

TE0808-05-6BI41-

S003

X

15eg

6eg_

1e

1i_

4gb

8gb

REV05

4GB

8GB

128MB

NA

CAO

Single Die DDR; U41 replaced with schottky diodes

TE0808-05-9BE21-

S005

A

9eg_

2i

1e_

4gb

REV05

4GB

128MB

NA

CAO

NA

TE0808-05-9BE21-

S004

AK

9eg_

2i

1e_

4gb

REV05

4GB

128MB

NA

1 mm connectors

NA

CAO

TE0808-05-

6BE21

9BE21-

AK

AZ

6eg

9eg_1e_

4gb

REV05

4GB

128MB

NA

1 mm connectors	NA
TE0808-05-9BE21-

LK

E

9eg_1e_

4gb

REV05

4GB

128MB

NA

1 mm connectors

NA	NA
TE0808-05-

9GI21

9BE21-

AK

F

9eg_

2i

1e_

4gb

REV05

4GB

128MB

NA

1 mm connectors	NA
TE0808-05-

BBE21

9BE21-

AK

KZ

15eg

9eg_1e_4gb

REV05

4GB

128MB

NA

1 mm connectors	NA
TE0808-05-9BE21-

S006

L

9eg_

2i

1e_

4gb

REV05

4GB

128MB

NA

1 mm connectors

NA

CAO

TE0808-05-9BE21-

S016

LK

9eg_1e_4gb

REV05

4GB

128MB

NA

1 mm connectors

NA

CAO

TE0808-05-

S018

9BE21-LZ

9eg_

2e

1e_4gb

REV05

4GB

128MB

NA

1 mm connectors

NA

CAO

TE0808-05-

S019

9BE81-A

9eg_

2e

1e_4gb

REV05

4GB

128MB

NA

CAO

NA

TE0808-05-

S021

9BI41-X

9eg_

2i

1i_

4gb

8gb

REV05

4GB

8GB

128MB

NA

CAO

Single Die DDR; U41 replaced with schottky diodes

TE0808-05-9GI21-

S022

A

6cg

9eg_

1e

2i_4gb

REV05

4GB

128MB

NA

CAO

NA

TE0808-05-

S026

9GI21-AK

9eg_2i_4gb

REV05

4GB

128MB

NA

CAO

NA

CAO: without PLL

TE0808-05-

9BE21

9GI21-

KZ

AZ

9eg_

1e

2i_4gb

REV05

4GB

128MB

NA

1 mm connectors

NA	NA
TE0808-05-

9BE21

9GI21-

LZ

C

9eg_

1e

2i_4gb

REV05

4GB

128MB

NA

1 mm connectors

NA	SoC without encryption

NA

TE0808-05-

9BE21

9GI21-

AK

E

9eg_

1e

2i_4gb

REV05

4GB

128MB

NA

1 mm connectors

NA	NA
TE0808-05-

9BE21

9GI21-

AZ

KZ

9eg_

1e

2i_4gb

REV05

4GB

128MB

NA

1 mm connectors

CAO

NA

CAO

TE0808-05-

9GI21

BBE21-

AZ

A

9eg

15eg_

2i

1e_4gb	REV05	4GB	128MB	NA	NA	NA
TE0808-05-BBE21-

AZ

AK	15eg_1e_4gb	REV05	4GB	128MB	NA	NA	NA
TE0808-05-

9BE81

BBE21-

A

AZ

9eg

15eg_1e_4gb	REV05	4GB	128MB	NA	NA	NA
TE0808-05-

S001

BBE21-E

9eg

15eg_1e_

8gb_D

4gb

REV05

8GB

4GB

128MB

NA

CAO

NA

CAO;Single Die DDR

TE0808-05-BBE21-

S020

L

9eg

15eg_

2i

1e_4gb

REV05

4GB

128MB

NA

CAO

1 mm connectors

CAO

NA

TE0808-05-

S025

BBE81-A

6eg

15eg_1e_4gb

_D

	REV05	4GB	128MB	NA	NA	NA
TE0808-05-BBE81-E	15eg_1e_4gb	REV05	4GB	128MB	NA

CAO

NA

CAO

NA

TE0808-05-BBE81-

S027

EK

9eg

15eg_

2i

1e_4gb

REV05

4GB

128MB

NA

CAO

NA

CAO

NA

TE0808-05-

S029

S001

9eg_

2i

1e_8gb_

4gb

D

REV05

4GB

8GB	128MB	NA	CAO	CAO;Single Die DDR
TE0808-05-

S035

S002	15eg_1e_4gb	REV05	4GB	128MB	NA	CAO	CAO
TE0808-05-

S036

S003	15eg_1e_4gb	REV05	4GB	128MB	NA	CAO	CAO
TE0808-05-

S038

S004

9eg_

1e

2i_4gb	REV05	4GB	128MB	NA	CAO	CAO
TE0808-05-

S039

S005

6eg

9eg_

1e

2i_4gb

REV05

4GB

128MB

NA

CAO

: without PLL

TE0808-05-

9GI21-KZ

S006	9eg_2i_4gb	REV05	4GB	128MB	NA	CAO	CAO
TE0808-05-

S041

S007

6eg

9eg_1e_4gb

_D

	REV05	4GB	128MB	NA	NA	CAO
TE0808-05-S014	9eg_1e_4gb	REV05	4GB	128MB	NA

CAO

NA

CAO

^*used as reference

Note: Design contains also Board Part Files for TE0808 only configuration, this board part files are not used for this reference design.

Design supports following carriers:

Scroll Title

anchor	Table_HWC
title-alignment	center
title	Hardware Carrier

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1tableStylingconfluencesortEnabledfalsecellHighlightingtrueCarrier ModelNotesTEBF0808^*Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended

^*used as reference

Additional HW Requirements:

Scroll Title

anchor	Table_AHW
title-alignment	center
title	Additional Hardware

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueAdditional HardwareNotesDisplay Port Monitor

Optional HW
Not all monitors are supported, also Adapter to other Standard can make trouble.
Design was tested with DELL U2412M

USB KeyboardOptional HW
Can be used to get access to console which is show on Display PortUSB StickOptional HW
USB was tested with USB memory stickSATA DiskOptional HWPCIe CardOptional HWETH cableOptional HW
Ethernet works with DHCP, but can be setup also manuallySD cardwith fat32 partition

^*used as reference

Content

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Notes :

content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

Scroll Title

anchor	Table_DS
title-alignment	center
title	Design sources

Scroll Table Layout

orientation	portrait
sortDirection	ASC
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TypeLocationNotesVivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_filesVivado Project will be generated by TE ScriptsVitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generationPetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration

TE0808-05-S016	9eg_1e_4gb	REV05	4GB	128MB	NA	CAO	CAO
TE0808-05-S018	9eg_2e_4gb	REV05	4GB	128MB	NA	CAO	CAO
TE0808-05-S019	9eg_2e_4gb	REV05	4GB	128MB	NA	CAO	CAO
TE0808-05-S020	9eg_2i_4gb	REV05	4GB	128MB	NA	CAO	CAO
TE0808-05-S021	9eg_2i_4gb	REV05	4GB	128MB	NA	CAO	CAO
TE0808-05-S022	6cg_1e_4gb	REV05	4GB	128MB	NA	CAO	CAO
TE0808-05-S025	6eg_1e_4gb_D	REV05	4GB	128MB	NA	CAO	CAO
TE0808-05-S026	9eg_2i_4gb	REV05	4GB	128MB	NA	CAO:Si5345 not assembled	CAO: without PLL
TE0808-05-S027	9eg_2i_4gb	REV05	4GB	128MB	NA	CAO	CAO
TE0808-05-S029	9eg_2i_4gb	REV05	4GB	128MB	NA	CAO	CAO
TE0808-05-S033	15eg_1e_4gb	REV05	4GB	128MB	NA	NA	CAO
TE0808-05-S035	15eg_1e_4gb	REV05	4GB	128MB	NA	CAO	CAO
TE0808-05-S036	15eg_1e_4gb	REV05	4GB	128MB	NA	CAO	CAO
TE0808-05-S038	9eg_1e_4gb	REV05	4GB	128MB	NA	CAO	CAO
TE0808-05-S039	6eg_1e_4gb	REV05	4GB	128MB	NA	CAO	CAO: without PLL
TE0808-05-S041	6eg_1e_4gb_D	REV05	4GB	128MB	NA	CAO	CAO

^*used as reference

Note: Design contains also Board Part Files for TE0808 only configuration, this board part files are not used for this reference design.

Design supports following carriers:

Additional Sources

Scroll Title

anchor	Table_ADSHWC
title-alignment	center
title	Additional design sourcesHardware Carrier

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TypeCarrier Model	Location	Notes
SI5345	<project folder>/misc/PLL/Si5345_B	SI5345 Project with current PLL Configuration
init.sh	<project folder>/misc/sd/	Additional initialization script for Linux

Prebuilt

TEBF0808^*

Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended

^*used as reference

Additional HW Requirements:

Notes :

prebuilt files

Template Table:PFPrebuilt filesConverted Software Application for MicroBlaze Processor Systems

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id	Comments

Scroll Title

anchor	Table_

title
AHW
title-alignment	center

Additional Hardware

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

File

File-Extension

Description

BIF-File

*.bif

File with description to generate Bin-File

BIN-File

*.bin

Flash Configuration File with Boot-Image (Zynq-FPGAs)

BIT-File

*.bit

FPGA (PL Part) Configuration File

Boot Script-File

*.scr

Distro Boot Script file

DebugProbes-File

*.ltx

Definition File for Vivado/Vivado Labtools Debugging Interface

Debian SD-Image

*.img

Debian Image for SD-Card

Diverse Reports

---

Report files in different formats

Device Tree

*.dts

Device tree (2 possible, one for u-boot and one for linux)

Hardware-Platform-Description-File

*.xsa

Exported Vivado hardware description file for Vitis and PetaLinux

LabTools Project-File

*.lpr

Vivado Labtools Project File

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

OS-Image

*.ub

Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)

Software-Application-File

*.elf

Software Application for Zynq or MicroBlaze Processor Systems

SREC-File

*.srec

Additional Hardware	Notes
Display Port Monitor	Optional HW Not all monitors are supported, also Adapter to other Standard can make trouble. Design was tested with DELL U2412M
USB Keyboard	Optional HW Can be used to get access to console which is show on Display Port
USB Stick	Optional HW USB was tested with USB memory stick
SATA Disk	Optional HW
PCIe Card	Optional HW
ETH cable	Optional HW Ethernet works with DHCP, but can be setup also manually
SD card	with fat32 partition

^*used as reference

Content

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hidden	true
id	Comments

Notes :

content of the zip file

For general structure and of the reference design, see Project Delivery - AMD devices

Design Sources

Scroll Title

anchor	Table_DS
title-alignment	center
title	Design sources

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Type	Location	Notes
Vivado	<project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files	Vivado Project will be generated by TE Scripts
Vitis	<project folder>\sw_lib	Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux	<project folder>\os\petalinux	PetaLinux template with current configuration

Additional Sources

Scroll Title

anchor	Table_PFADS
title-alignment	center
title	Prebuilt files (only on ZIP with prebult content)Additional design sources

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orientation	portrait
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style
widths
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FileTypeFile-Extension	Location	DescriptionNotes	BIF-File
SI5345	<project folder>/misc/PLL/	SI5345 Project with current PLL Configuration
init.sh	<project folder>/misc/sd/	Additional initialization script for Linux

Prebuilt

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Notes :

prebuilt files

Template Table:

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title-alignment	center
title	Prebuilt files

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
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File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
Boot Script-File	*.scr	Distro Boot Script file
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image	*.img	Debian Image for SD-Card
Diverse Reports	---	Report files in different formats
Device Tree	*.dts	Device tree (2 possible, one for u-boot and one for linux)
Hardware-Platform-Description-File	*.xsa	Exported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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hidden	true
id	Comments

Important set new Vivado version link on every Design update of new vivado version!
Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

Reference Design is available on:

TE0808 "StarterKit" Reference Design

Design Flow

Scroll Ignore

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

- SREC-File
  *.srec
  Converted Software Application for MicroBlaze Processor Systems

Scroll Title

anchor	Table_PF
title-alignment	center
title	Prebuilt files (only on ZIP with prebult content)

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
Boot Script-File	*.scr	Distro Boot Script file
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
Device Tree	*.dts	Device tree (2 possible, one for u-boot and one for linux)
Hardware-Platform-Description-File	*.xsa	Exported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

Page properties

hidden	true
id	Comments

Important set new Vivado version link on every Design update of new vivado version!
Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

Reference Design is available on:

TE0808 "StarterKit" Reference Design

Design Flow

Scroll Ignore

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

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hidden	true
id	Comments

Notes :

Basic Design Steps
Add/ Remove project specific description

Note
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

Launch

Scroll Ignore

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scroll-docbook	true
scroll-eclipsehelp	true
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scroll-html	true

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Note:

Programming and Startup procedure

For basic board setup, LEDs... see: TEBF0808 Getting Started

Programming

Note
Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
Press 0 and enter to start "Module Selection Guide"
1. Select assembly version
2. Validate selection
3. Select create and open delivery binary folder
  Info
  Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

QSPI-Boot mode

Option for Boot.bin on QSPI Flash.

Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block
language py
theme Midnight
title run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
TE::pr_program_flash -swapp hello_te0808
Set Boot Mode to QSPI-Boot
- Depends on Carrier, see carrier TRM.
- TEBF0808 change automatically the Boot Mode to SD, if SD is inserted, optional CPLD Firmware without Boot Mode changing for microSD Slot is available on the download area

SD-Boot mode

Copy image.ub, boot.scr and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)

Select SD Card as Boot Mode (or QSPI - depending on step 1)

Info
Note: See TRM of the Carrier, which is used.

Tip

Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scr

(Optional with TEBF0808) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
(Optional with TEBF0808) Connect SATA Disc
(Optional with TEBF0808) Connect Display Port Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
(Optional with TEBF0808) Connect Network Cable

Power On PCB

Expand

title	boot process

1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

Linux

Open Serial Console (e.g. putty)
- Speed: 115200
- select COM Port
  Info
  Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

Linux Console:

Code Block

language	bash
theme	Midnight

# password default disabled
petalinux with 2021.2 petalinux release
petalinux login: root
login: root
Password: root

Info
Note: Wait until Linux boot finished

You can use Linux shell now.

Code Block

language	bash
theme	Midnight

i2cdetect -y -r 0	(check I2C 0 Bus, replace 0 with other bus number is also possible)
dmesg | grep rtc	(RTC check)
udhcpc				(ETH0 check)
lsusb				(USB check)
lspci               (PCIe check)

Option Features
- Webserver to get access to ZynqMP
  - insert IP on web browser to start web interface
- init.sh scripts
  - add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

Vivado Hardware Manager

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Note:

Add picture of HW Manager
add notes for the signal either groups or topics, for example:
Control:
- add controllable IOs with short notes..
Monitoring:
- add short notes for signals which will be monitored only
- SI5338 CLKs:
  - Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
  - expected CLK Frequency...

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).

RGPIO Interface (Important: CPLD Firmware REV07 or newer is needed) for Control and Monitoring:
- Set Enable to send Write date over RGPIO interface.
  - Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD
    - Buttons, LEDs, Status...

Control:
- LEDs: XMOD 2 (without green dot) and HD LED are accessible.
- CAN_S

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anchor	Figure_VHM
title-alignment	center
title	Vivado Hardware Manager

System Design - Vivado

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Note:

Description of Block Design, Constrains... BD Pictures from Export...

Block Design

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title-alignment	center
title	Block Design

PS Interfaces

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Note:

optional for Zynq / ZynqMP only
add basic PS configuration

Activated interfaces:

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anchor	Table_PSI
title-alignment	center
title	PS Interfaces

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Type	Note
DDR
QSPI	MIO
SD0	MIO
SD1	MIO
CAN0	EMIO
I2C0	MIO
PJTAG0	MIO
UART0	MIO
GPIO0	MIO
SWDT0..1
TTC0..3
GEM3	MIO
USB0	MIO/GTP
PCIe	MIO/GTP
SATA	GTP
Display Port	EMIO/GTP

Constrains

Basic module constrains

Code Block

language	ruby
title	_i_bitgen.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Code Block

language	ruby
title	_i_io.xdc

#System Controller IP
  #LED_HD SC0 J3:31
  #LED_XMOD SC17 J3:48 
  #CAN RX SC19 J3:52 B47_L2_P in
  #CAN TX SC18 J3:50 B47_L2_N out 
  #CAN S  SC16 J3:46 B47_L3_N out
#HDIO_SC1    K14
#HDIO_SC2    H13
#HDIO_SC3    H14
#HDIO_SC4    F13



#HDIO_SC0    J14
set_property PACKAGE_PIN J14 [get_ports BASE_sc0]
#HDIO_SC5    G13
set_property PACKAGE_PIN G13 [get_ports BASE_sc5]
#HDIO_SC6    J15
set_property PACKAGE_PIN J15 [get_ports BASE_sc6]
#HDIO_SC7    K15
set_property PACKAGE_PIN K15 [get_ports BASE_sc7]
#HDIO_SC10   A15
set_property PACKAGE_PIN A15 [get_ports BASE_sc10_io]
#HDIO_SC11   B15
set_property PACKAGE_PIN B15 [get_ports BASE_sc11]
#HDIO_SC12   C13
set_property PACKAGE_PIN C13 [get_ports BASE_sc12]
#HDIO_SC13   C14
set_property PACKAGE_PIN C14 [get_ports BASE_sc13]
#HDIO_SC14   E13
set_property PACKAGE_PIN E13 [get_ports BASE_sc14]
#HDIO_SC15   E14
set_property PACKAGE_PIN E14 [get_ports BASE_sc15]
#HDIO_SC16   A13
set_property PACKAGE_PIN A13 [get_ports BASE_sc16]
#HDIO_SC17   B13
set_property PACKAGE_PIN B13 [get_ports BASE_sc17]
#HDIO_SC18   A14
set_property PACKAGE_PIN A14 [get_ports BASE_sc18]
#HDIO_SC19   B14
set_property PACKAGE_PIN B14 [get_ports BASE_sc19]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]


# Audio Codec
#LRCLK		  J3:49 B47_L9_N
#BCLK		    J3:51 B47_L9_P
#DAC_SDATA	  J3:53 B47_L7_N
#ADC_SDATA	  J3:55 B47_L7_P

#LRCLK G14
set_property PACKAGE_PIN G14 [get_ports I2S_lrclk ]
#BCLK G15
set_property PACKAGE_PIN G15 [get_ports I2S_bclk ]
#DAC_SDATA E15
set_property PACKAGE_PIN E15 [get_ports I2S_sdin ]
#ADC_SDATA F15
set_property PACKAGE_PIN F15 [get_ports I2S_sdout ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ]

Software Design - Vitis

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Note:

optional chapter separate
sections for different apps

For Vitis project creation, follow instructions from:

Vitis

Application

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----------------------------------------------------------

FPGA Example

----------------------------------------------------------

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 20212023.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

Modified Files: blconfig.h, bootloader.c
Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 20212023.2 xilisf_v5_11

Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

fsbl

TE modified 2021.2 FSBL

General:

----------------------------------------------------------

fsbl

TE modified 2023.2 FSBL

General:

Modified Files: main.c, fsbl_hooks.h/.c Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c (for hooks and board)
General Changes:
- Display FSBL Banner and Device ID

Module Specific:

Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY

fsbl_flash

TE modified 2021.2 FSBL

General:

Modified Files: main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2021.2 FSBL

General:

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2023.2 FSBL

General:

Modified Files: xfsbl_main.c, xfsblModified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
General Changes:
- Display FSBL Banner and Device Name

Module Specific:

Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2021.2 FSBL

General:

Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

----------------------------------------------------------

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Template location: "<project folder>\sw_lib\sw_apps\"

zynqmp_fsbl

TE modified 20212023.2 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
General Changes:
- Display FSBL Banner and Device Name

Module Specific:

Add Files: all TE Files start with te_*
- Si5345 Configuration
- OTG+PCIe Reset over MIO
- I2C MUX for EEPROM MAC

zynqmp_fsbl_flash

TE modified 2021.2 FSBL

General:

Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0808

Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design - PetaLinux

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Note:

optional chapter separate
sections for linux
Add "No changes." or "Activate: and add List"

For PetaLinux installation and project creation, follow instructions from:

PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

select SD default instead of eMMC:
- CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
generate u-boot.dtb:
add new flash partition for bootscr and sizing
- CONFIG_SUBSYSTEM_UBOOT_EXT_DTB=y
add new flash partition for bootscr and sizing
- FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0PART1_SIZE=0xA000000x3000000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x20000000x40000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
- CONFIG_SUBSYSTEM_UBOOT_QSPI_FIT_IMAGE_OFFSET=0xA00000
- CONFIG_SUBSYSTEM_UBOOT_QSPI_FIT_IMAGE_SIZE=0x3000000
Identification
- CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
- CONFIG_SUBSYSTEM_PRODUCT="TE0808_TEBF0808"

U-Boot

Start with petalinux-config -c u-boot

Changes:

MAC from eeprom together with uboot and device tree settings:CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
- CONFIG_ENV_OVERWRITE=y
- CONFIG_SYS_I2C_EEPROM_ADDR=0x50NVMEM=y
- CONFIG_SYS_I2C_EEPROM_BUS=7DM_RTC=y (needed for nvmem driver because of bug in uboot)
Boot Modes:
- CONFIG_QSPI_BOOT=y
- CONFIG_SD_BOOT=y
- # CONFIG_ENV_IS_IN_NAND FAT is not set
- CONFIG_ENV_IS_IN_NAND is not set
- CONFIG_ENV_IS_IN_SPI_FLASH is not set
- CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000=0x3A40000
Identification
- CONFIG_IDENT_STRING=" TE0808_TEBF0808"

Change platform-top.h:

Code Block

language	js

#no changes

Device Tree

Code Block

language	js
title	project-spec\meta-user\recipes-bsp\device-tree\files\system-user.dtsi

/include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; }; }; /*------------------ gtr --------------------*/ //https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver / { refclk3:psgtr_dp_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <27000000>; }; refclk2:psgtr_pcie_usb_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <100000000>; }; refclk1:psgtr_sata_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <150000000>; }; //refclk0:psgtr_unused_clock { // compatible = "fixed-clock"; // #clock-cells = <0x00>; // clock-frequency = <100000000>; //}; }; &psgtr { clocks = <&refclk1 &refclk2 &refclk3>; /* ref clk instances used per lane */ clock-names = "ref1\0ref2\0ref3"; }; /*------------------ SD --------------------*/ &sdhci0 { // disable-wp; no-1-8-v; }; &sdhci1 { // disable-wp; no-1-8-v; }; /*------------------ USB --------------------*/ &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; phy-names = "usb2-phy","usb3-phy"; maximum-speed = "super-speed"; }; /*------------------ ETH PHY --------------------*/ &gem3 { phy-handle = <&phy0>; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /*------------------ QSPI --------------------*/ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /*------------------ I2C --------------------*/ &i2c0 { i2cswitch@73 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x73>; i2c-mux-idle-disconnect; i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1 { // SFP TEBF0808 PCF8574DWR #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { // PCIe #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // SFP1 TEBF0808 #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 {// SFP2 TEBF0808 #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { // TEBF0808 EEPROM #address-cells = <1>; #size-cells = <0>; reg = <5>; eeprom: eeprom@50 { compatible = "atmel,24c08"; reg = <0x50>; }; }; i2c@6 { // TEBF0808 FMC #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { // TEBF0808 USB HUB #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2cswitch@77 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x77>; i2c-mux-idle-disconnect; i2c@0 { // TEBF0808 PMOD P1 #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1 { // i2c Audio Codec #address-cells = <1>; #size-cells = <0>; reg = <1>; /* adau1761: adau1761@38 { compatible = "adi,adau1761"; reg = <0x38>; }; */ }; i2c@2 { // TEBF0808 Firefly A #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // TEBF0808 Firefly B #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 { //Module PLL Si5338 or SI5345 #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { //TEBF0808 CPLD #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { //TEBF0808 Firefly PCF8574DWR #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { // TEBF0808 PMOD P3 #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; };

Device Tree

Code Block

language	js
title	project-spec\meta-user\recipes-bsp\uboot-device-tree\files\system-user.dtsi

/include/ "system-conf.dtsi"
/ {
  chosen {
    xlnx,eeprom = &eeprom;
  };
};


/*------------------ gtr --------------------*/

//https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
 
/ {
  refclk3:psgtr_dp_clock {
          compatible = "fixed-clock";
          #clock-cells = <0x00>;
          clock-frequency = <27000000>;
  };
   
   refclk2:psgtr_pcie_usb_clock {
           compatible = "fixed-clock";
           #clock-cells = <0x00>;
           clock-frequency = <100000000>;
   };
    
  refclk1:psgtr_sata_clock {
          compatible = "fixed-clock";
          #clock-cells = <0x00>;
          clock-frequency = <150000000>;
  };
    
  //refclk0:psgtr_unused_clock {
  //        compatible = "fixed-clock";
  //        #clock-cells = <0x00>;
  //        clock-frequency = <100000000>;
  //};
};
 
&psgtr {
  clocks = <&refclk1 &refclk2 &refclk3>;
  /* ref clk instances used per lane */
  clock-names = "ref1\0ref2\0ref3";
};
 
 
 
/*-------------------- SD0 SDeMMC --------------------*/
&sdhci0 {
    // disablebus-wp;width
    no-1-8-vbus-width = <8>;
 
};
 
/*-------------------- SD1 SD2.0 ----------------*/
&sdhci1 {
    // disable-wp;
    no-1-8-v;
 
};
 
 
/*------------------- USB --------------------*/
&dwc3_0 {
    //status = "okay";
    dr_mode = "host";
    //snps,usb3_lpm_capable;
    //snps,dis_u3_susphy_quirk;
    //snps,dis_u2_susphy_quirk;
    //phy-names = "usb2-phy","usb3-phy";
    //maximum-speed = "super-speed";
};


/*------------------ ETH PHY --------------------*/
&gem3 {
    phy-handle = <&phy0>;
    phy0: phy0@1 {
        device_type = "ethernet-phy";
        reg = <1>;
    };
};
 

/*------------------ QSPI --------------------*/
&qspi {/delete-property/ local-mac-address;
    #addressphy-cellshandle = <1><&phy0>;

    #sizenvmem-cells = <0><&eth0_addr>;
    statusnvmem-cell-names = "okaymac-address";

    flash0phy0: flash@0phy0@1 {
        compatibledevice_type = "jedec,spiethernet-norphy";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};


/*------------------ SATA I2CPHY --------------------*/
&i2c0sata {

    i2cswitch@73 { // u ceva,p0-burst-params = <0x13084a06>;
        compatible = "nxp,pca9548"ceva,p0-cominit-params = <0x18401828>;
        #address-cellsceva,p0-comwake-params = <1><0x614080e>;
        #size-cellsceva,p0-retry-params = <0><0x96a43ffc>;
        reg ceva,p1-burst-params = <0x73><0x13084a06>;
     ceva,p1-cominit-params   i2c-mux-idle-disconnect= <0x18401828>;
     ceva,p1-comwake-params = <0x614080e>;
 i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
            #address-cells = <1>;
      ceva,p1-retry-params = <0x96a43ffc>;

};


/*-------------------- QSPI ---------------------*/
&qspi {
    num-cs = <2>;

    flash@0 {
       #size-cells compatible = <0>"jedec,spi-nor";
            reg = <0>, <1>;
         };
        i2c@1 { // SFP TEBF0808 PCF8574DWR
    parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 2* 16MB --> dummy for all types of this QSPI type */

        #address-cellsspi-rx-bus-width = <1><4>;
            #size-cellsspi-tx-bus-width = <0><4>;
        // for variants populated reg = <1>;with n25qu512
        };
        i2c@2 { // PCIe
 spi-max-frequency = <108000000>; // max. frequency also depends on the QSPI chip
           #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
// here 108MHz for N25Q512A (Fast Read Quad };
IO STR, 8 Dummy Cycles, quad SPI  i2c@3protocol)
 { // SFP1 TEBF0808
    
        #address-cells = <1>;
            #size-cells = <0><1>;
        
    reg = <3>;
 };
};


/*------------------ I2C --------------------*/
&i2c0 {
    i2cswitch@73 { // };u
        i2c@4 {// SFP2 TEBF0808
  compatible = "nxp,pca9548";
        #address-cells = <1>;
            #size-cells = <0>;
            reg = <4><0x73>;
        }i2c-mux-idle-disconnect;
        i2c@5i2c@0 { // MCLK TEBF0808 EEPROM
            #address-cells = <1>;SI5338A, 570FBB000290DG_unassembled
            #size-cellsreg = <0>;
            reg = <5>};
            eeprom: eeprom@50 {
                compatible = "atmel,24c08";i2c@1 { // SFP TEBF0808 PCF8574DWR
                reg = <0x50>;
              }<1>;
        };
        i2c@6i2c@2 { // TEBF0808 FMC PCIe
            #address-cellsreg = <1><2>;
        };
        i2c@3 { #size-cells = <0>;// SFP1 TEBF0808
            reg = <6><3>;
        };
        i2c@7i2c@4 { // SFP2 TEBF0808 USB HUB
            #address-cellsreg = <1><4>;
        };
      #size-cells = <0>;  i2c@5 { // TEBF0808 EEPROM
            reg = <7><5>;
        };
    };
eeprom: eeprom@50 {
     i2cswitch@77 { // u
        compatible = "nxpmicrochip,pca954824aa025";
        #address-cells = <1>;
  , "atmel,24c02";
      #size-cells = <0>;
        reg = <0x77><0x50>;
        i2c-mux-idle-disconnect;
        i2c@0 {
 // TEBF0808 PMOD P1
            #address-cells = <1>;
                #size-cells = <0><1>;
              reg = <0>;  eth0_addr: eth-mac-addr@FA {
        };
        i2c@1 { //reg i2c= Audio<0xFA Codec0x06>;
              #address-cells = <1>};
            #size-cells = <0>};
            reg = <1>};
        i2c@6 { // TEBF0808 /*FMC
            adau1761:reg adau1761@38= {<6>;
        };
        compatiblei2c@7 = "adi,adau1761";
   { // TEBF0808 USB HUB
             reg = <0x38><7>;
        };
    };
    i2cswitch@77 { // u
     */
   compatible     }= "nxp,pca9548";
        i2c@2reg { // TEBF0808 Firefly A= <0x77>;
            #address-cells = <1>i2c-mux-idle-disconnect;
        i2c@0 { // TEBF0808 #size-cells = <0>;PMOD P1
            reg = <2><0>;
        };
        i2c@3i2c@1 { // TEBF0808i2c FireflyAudio BCodec
            #address-cellsreg = <1>;
            #size-cells = <0>;/*
            regadau1761: =adau1761@38 <3>;{
        };
        i2c@4compatible { //Module PLL Si5338 or SI5345
= "adi,adau1761";
                #address-cellsreg = <1><0x38>;
            #size-cells = <0>};
            reg = <4>;*/
        };
        i2c@5i2c@2 { // TEBF0808 CPLD
Firefly A
            reg = <2>;
      #address-cells = <1>};
        i2c@3 { // TEBF0808 #size-cells = <0>;Firefly B
            reg = <5><3>;
        };
        i2c@6i2c@4 { //TEBF0808 Firefly PCF8574DWRModule PLL Si5338 or SI5345
            #address-cellsreg = <1><4>;
        };
        i2c@5 #size-cells = <0>;{ //TEBF0808 CPLD
            reg = <6><5>;
        };
        i2c@7i2c@6 { // TEBF0808 PMODFirefly P3PCF8574DWR
            #address-cellsreg = <1><6>;
        };
         #size-cells = <0>;i2c@7 { // TEBF0808 PMOD P3
            reg = <7>;
        };
    };
};

FSBL patch

Must be add manually, see template

Kernel

Start with petalinux-config -c kernel

Changes:

Only needed to fix JTAG Debug issue:# CONFIG_CPU_IDLE is not set
- # CONFIG_CPU_FREQ is not setCONFIG_EDAC_CORTEX_ARM64=yset
Support PCIe memory card
- CONFIG_NVME_CORE=y
- CONFIG_BLK_DEV_NVME=y
- # CONFIG_NVME_MULTIPATH is not set
- # CONFIG_NVME_VERBOSE_ERRORS is not set
- # CONFIG_NVME_HWMON is not set
- # CONFIG_NVME_TCP AUTH is not set
- CONFIG_NVME_TARGET=y
- # CONFIG_NVME_TARGET_PASSTHRU is not set
- # CONFIG_NVME_TARGET_LOOP is not set
- # CONFIG_NVME_TARGET_FC is not set
- # CONFIG_NVME_TARGET_TCP is not set
- CONFIG_SATA_AHCI=y
- CONFIG_SATA_MOBILE_LPM_POLICY=0
- CONFIG_NVM=y
- CONFIG_NVM_PBLK=y
- CONFIG_NVM_PBLK_DEBUG=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

For web server app:

CONFIG_busybox-httpd=y

- is not set
- # CONFIG_NVME_TARGET_AUTH is not set
- CONFIG_SATA_AHCI=y
- CONFIG_SATA_MOBILE_LPM_POLICY=0

Rootfs

Start with petalinux-config -c rootfs

Changes:

For web server app:
- CONFIG_busybox-httpd=y
For additional test tools only:
- CONFIG_i2c-tools=y
- CONFIG_packagegroup-petalinux-utils=y (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
For auto login:
- CONFIG_imagefeature-serial-autologin-root=y

FSBL patch (alternative for vitis fsbl trenz patch)

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"

Note

Identical to adjustments made in zynqmp_fsbl

te_* files are identical to files in "<project folder>\sw_lib\sw_apps\zynqmp_fsbl\src" except for the PLL files (SI5345) which depend on PLL revision. The PLL files may have to be copied again manually into the appropriate petalinux folder "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw\fsbl-firmware\git\lib\sw_apps\zynqmp_fsbl\src"
Petalinux Troubleshoot#Petalinux2023.2

Boot.scr patch

Petalinux template with Trenz debug log prints, see "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\u-boot"

For additional test tools only:

CONFIG_i2c-tools=y

CONFIG_packagegroup-petalinux-utils=y (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)

Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application suitable for ZynqMP access. Need busybox-httpd

Additional Software

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Note:

Add description for other Software, for example SI CLK Builder ...
SI5338 and SI5345 also Link to:
- Si5345
- Si5338

SI5345

File location "<project folder>/misc/PLL/Si5345_B*/Si5345-*.slabtimeproj"

General documentation how you work with these project will be available on Si5345

Appx. A: Change History and Legal Notices

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Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

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Authors

Description

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infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

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infoType	Current version
prefix	v.
type	Flat

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infoType	Modified by
type	Flat

bugfix QSPI partition for image.ub in Linux
update device tree

2024-05-29

v.60

Manuela Strücker

new assembly variants
update petalinux
bugfix board files for eMMC

2024-03-14

v.59

Manuela Strücker

2023.2 release
new assembly variants

2023-06-13

v.58

Manuela Strücker

added chapter FSBL patch
added alternative generation of BOOT.bin in Petalinux (chapter Design flow)

2023-06-01

v.56

Manuela Strücker

2022.2 release
new assembly variants

2023-04-13

v.55

Manuela Strücker

script update
new assembly variants

2022-09-29

v.53

Manuela Strücker

new assembly variants

2022-09-29

v.51

Manuela Strücker

update board part files compatible to Vivado 2021.2.1

2022-09-06

v.50

Manuela Strücker

typo

2022-03.16

v.48

Manuela Strücker

2021.2 release
update board files

2022-02-03

v.47

John Hartfiel

Typo correction on key features section

2021-07-15

v.46

Manuela Strücker

Document Style update

2021-05-12

v.44

John Hartfiel

update board files
update design

2021-02-05

v.43

John Hartfiel

2020.2 release
document style update

2020-11-06

v.41

John Hartfiel

typo bugfix for programming part

2020-09-29

v.40

John Hartfiel

new assembly variants

2020-03-25

v.37

John Hartfiel

script update

2020-02-25

v.35

John Hartfiel

Update requirement section

2020-01-23

v.34

John Hartfiel

new assembly variants
Release 2019.2

2019-08-09

v.32

John Hartfiel

new assembly variants
small FSBL update
minor document style update

2019-05-07

v.29

John Hartfiel

Release 2018.3

2018-08-09

v.27

John Hartfiel

Release 2018.2

2018-05-25

v.21

John Hartfiel

Solved known issues

2018-04-30

v.19

John Hartfiel

Update known issues

2018-03-29

v.18

John Hartfiel

New assembly variant

2018-02-08

v.16

John Hartfiel

Solved known issues

2018-01-29

v.10

John Hartfiel

Update known issues

2018-01-18

v.8

John Hartfiel

Update documentation only

2018-01-17

v.7

John Hartfiel

Update design

2018-01-15

v.4

John Hartfiel

Release 2017.4

2017-12-20

v.2

John Hartfiel

Release 2017.2

All

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type	Flat

Legal Notices

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	IN:Legal Notices

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Trenz Electronic Documentation

Page History

Versions Compared

Old Version 54

New Version Current

Key

Overview

Key Features

Revision History

Revision History

Release Notes and Know Issues

Release Notes and Know Issues

Requirements

Software

Requirements

Software

Hardware

Hardware

Content

Design Sources

Additional Sources

Prebuilt

Content

Design Sources

Additional Sources

Prebuilt

Download

Design Flow

Download

Design Flow

Launch

Programming

Get prebuilt boot binaries

QSPI-Boot mode

SD-Boot mode

JTAG

Usage

Linux

Vivado Hardware Manager

System Design - Vivado

Block Design

PS Interfaces

Constrains

Basic module constrains

Design specific constrain

Software Design - Vitis

Application

scu

srec_spi_bootloader

xilisf_v5_11

fsbl

fsbl

fsbl_flash

zynqmp_fsbl

zynqmp_fsbl

zynqmp_fsbl_flash

zynqmp_pmufw

hello_te0820

u-boot

zynqmp_fsbl

zynqmp_fsbl_flash

zynqmp_pmufw

hello_te0808

u-boot

Software Design - PetaLinux

Config

U-Boot

Device Tree

Device Tree

FSBL patch

Kernel

Rootfs

Rootfs

FSBL patch (alternative for vitis fsbl trenz patch)

Boot.scr patch

Applications

startup

webfwu

Additional Software

SI5345