Page History

Overview

Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

Key Features

Revision History

Release Notes and Know Issues

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Design supports following carriers:

^*used as reference

Additional HW Requirements:

Optional HW
Not all monitors are supported, also Adapter to other Standard can make trouble.
Design was tested with DELL U2412M

Design supports following carriers:

^*used as reference

Content

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

Additional HW Requirements:

Content

For general structure and of the reference design, see Project Delivery - AMD devices

Design Sources

Additional Sources

Prebuilt

• • Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true File File-Extension Description BIF-File *.bif File with description to generate Bin-File BIN-File *.bin Flash Configuration File with Boot-Image (Zynq-FPGAs) BIT-File *.bit FPGA (PL Part) Configuration File Boot Script-File *.scr Distro Boot Script file DebugProbes-File *.ltx Definition File for Vivado/Vivado Labtools Debugging Interface

• • Debian SD-Image *.img Debian Image for SD-Card Diverse Reports --- Report files in different formats Device Tree *.dts Device tree (2 possible, one for u-boot and one for linux) Hardware-Platform-Description-File *.xsa Exported Vivado hardware description file for Vitis and PetaLinux LabTools Project-File *.lpr Vivado Labtools Project File MCS-File *.mcs Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) MMI-File *.mmi File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) OS-Image *.ub Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) Software-Application-File *.elf Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

• TE0808 "StarterKit" Reference Design

Design Flow

Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

• TE0808 "StarterKit" Reference Design

Design Flow

See also:

• AMD Development Tools#XilinxSoftware-BasicUserGuides
• Vivado Projects - TE Reference Design
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

   Code Block
   language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh
   ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> ----

See also:

• AMD Development Tools#XilinxSoftware-BasicUserGuides
• Vivado Projects - TE Reference Design
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

   Code Block
   language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh
   ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):

   
   

2. Press 0 and enter to start "Module Selection Guide"
3. Create project and follow instructions of the product selection guide, settings file will be configured automatically during this process.
   

   • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

     Note
     Note: Select correct one, see also Vivado Board Part Flow Important: Use Board Part Files, which ends with *_tebf0808

     
     

4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

   Code Block
   language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
   TE::hw_build_design -export_prebuilt

   
   

   Info
   Using Vivado GUI is the same, except file export to prebuilt folder.

5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
   • use TE Template from "<project folder>\os\petalinux"

   • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

   • The build images are located in the "<plnx-proj-root>/images/linux" directory

6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr
   

7. the same, except file export to prebuilt folder.

   
   

8. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
   • use TE Template from "<project folder>\os\petalinux"

   • use exported .xsa file from

   Copy PetaLinux build image files to prebuilt folder
   • copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
     
   Info"<project folder>\prebuilt\os\petalinux\<ddr size>" or

   • "<project folder>\prebuilt\

   os\petalinux

   • hardware\<short name>

   " Page properties

   hidden	true
   id	Comments

   • " . Note: HW Export from Vivado GUI creates another path as default workspace.

   • The build images are located in the

   This step depends on Xilinx Device/Hardware

   for Zynq-7000 series

   copy u-boot.elf, system.dtb, image.ub and boot.scr from

   • "<plnx-proj-root>/images/linux" directory

9. Configure the boot.scr file as needed, see Distro Boot with Boot.scr
   

10. Generate Programming Files with Vitis (recommended)
    
    1. Copy PetaLinux build image files to prebuilt folder
    for ZynqMP
    1. • copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
    for Microblaze
    1. • 
         
    • ...

    1. Generate Programming Files

    with Vitis

    1. Code Block
       language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
       TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)

       
       

       Note
       TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

       
       

11. Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart

Launch

For basic board setup, LEDs... see: TEBF0808 Getting Started

Programming

Get prebuilt boot binaries

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection

   3. Select create and open delivery binary folder

      Info
      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

      
      

QSPI-Boot mode

Option for Boot.bin on QSPI Flash.

1. Connect JTAG and power on carrier with module

2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

   Code Block
   language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
   TE::pr_program_flash -swapp hello_te0808

   
   

3. Set Boot Mode to QSPI-Boot
   
   • Depends on Carrier, see carrier TRM.
   • TEBF0808 change automatically the Boot Mode to SD, if SD is inserted, optional CPLD Firmware without Boot Mode changing for microSD Slot is available on the download area

SD-Boot mode

1. Copy image.ub, boot.scr and Boot.bin on SD
   
   • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
   • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
2. Set Boot Mode to SD-Boot.
   • Depends on Carrier, see carrier TRM.
3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)

3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

   Info
   Note: See TRM of the Carrier, which is used.

   
   

   Tip

   Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. The boot options described above describe the common boot processes for this hardware; other boot options are possible. For more information see Distro Boot with Boot.scr

   
   

4. (Optional with TEBF0808) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
5. (Optional with TEBF0808) Connect SATA Disc
6. (Optional with TEBF0808) Connect Display Port Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
7. (Optional with TEBF0808) Connect Network Cable

8. Power On PCB

   Expand
   title boot process
   1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR

   
   

Linux

1. Open Serial Console (e.g. putty)
   
   • Speed: 115200

   • select COM Port

     Info
     Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

     
     

2. Linux Console:
   

   Code Block
   language bash theme Midnight
   # password disabled petalinux login: root Password: root

   
   

   Info
   Note: Wait until Linux boot finished

   
   

3. You can use Linux shell now.
   

   Code Block
   language bash theme Midnight
   i2cdetect -y -r 0 (check I2C 0 Bus, replace 0 with other bus number is also possible) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check) lspci (PCIe check)

   
   

4. Option Features

   • Webserver to get access to ZynqMP
     • insert IP on web browser to start web interface
   • init.sh scripts
     • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

Vivado Hardware Manager

• RGPIO Interface (Important: CPLD Firmware REV07 or newer is needed) for Control and Monitoring:
  

  • Set Enable to send Write date over RGPIO interface. 
    • Important use CPLD Firmware REV07 or newer: https://wiki.trenz-electronic.de/display/PD/TEBF0808+CPLD
      • Buttons, LEDs, Status...

• Control:
  • LEDs: XMOD 2 (without green dot) and HD LED are accessible.
  • CAN_S
    

System Design - Vivado

Block Design

Scroll Title
anchor Figure_BD title-alignment center title Block Design

PS Interfaces

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

#System Controller IP
  #LED_HD SC0 J3:31
  #LED_XMOD SC17 J3:48 
  #CAN RX SC19 J3:52 B47_L2_P in
  #CAN TX SC18 J3:50 B47_L2_N out 
  #CAN S  SC16 J3:46 B47_L3_N out
#HDIO_SC1    K14
#HDIO_SC2    H13
#HDIO_SC3    H14
#HDIO_SC4    F13



#HDIO_SC0    J14
set_property PACKAGE_PIN J14 [get_ports BASE_sc0]
#HDIO_SC5    G13
set_property PACKAGE_PIN G13 [get_ports BASE_sc5]
#HDIO_SC6    J15
set_property PACKAGE_PIN J15 [get_ports BASE_sc6]
#HDIO_SC7    K15
set_property PACKAGE_PIN K15 [get_ports BASE_sc7]
#HDIO_SC10   A15
set_property PACKAGE_PIN A15 [get_ports BASE_sc10_io]
#HDIO_SC11   B15
set_property PACKAGE_PIN B15 [get_ports BASE_sc11]
#HDIO_SC12   C13
set_property PACKAGE_PIN C13 [get_ports BASE_sc12]
#HDIO_SC13   C14
set_property PACKAGE_PIN C14 [get_ports BASE_sc13]
#HDIO_SC14   E13
set_property PACKAGE_PIN E13 [get_ports BASE_sc14]
#HDIO_SC15   E14
set_property PACKAGE_PIN E14 [get_ports BASE_sc15]
#HDIO_SC16   A13
set_property PACKAGE_PIN A13 [get_ports BASE_sc16]
#HDIO_SC17   B13
set_property PACKAGE_PIN B13 [get_ports BASE_sc17]
#HDIO_SC18   A14
set_property PACKAGE_PIN A14 [get_ports BASE_sc18]
#HDIO_SC19   B14
set_property PACKAGE_PIN B14 [get_ports BASE_sc19]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]


# Audio Codec
#LRCLK		  J3:49 B47_L9_N
#BCLK		  J3:51 B47_L9_P
#DAC_SDATA	  J3:53 B47_L7_N
#ADC_SDATA	  J3:55 B47_L7_P

#LRCLK G14
set_property PACKAGE_PIN G14 [get_ports I2S_lrclk ]
#BCLK G15
set_property PACKAGE_PIN G15 [get_ports I2S_bclk ]
#DAC_SDATA E15
set_property PACKAGE_PIN E15 [get_ports I2S_sdin ]
#ADC_SDATA F15
set_property PACKAGE_PIN F15 [get_ports I2S_sdout ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ]

Software Design - Vitis

For Vitis project creation, follow instructions from:

Vitis

Application

zynqmp_fsbl

TE modified 20222023.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
• Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
• General Changes: 
  
  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*
  
  • Si5345 Configuration
  • OTG+PCIe Reset over MIO
  • I2C MUX for EEPROM MAC

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0808

Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design -  PetaLinux

• PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• select SD default instead of eMMC:
  • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
• add new flash partition for bootscr and sizing
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x20000000x3000000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x40000
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
  • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000
  • CONFIG_SUBSYSTEM_UBOOT_QSPI_FIT_IMAGE_OFFSET=0xA00000
  • CONFIG_SUBSYSTEM_UBOOT_QSPI_FIT_IMAGE_SIZE=0x3000000
• Identification
  • CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
  • CONFIG_SUBSYSTEM_PRODUCT="TE0808_TEBF0808"

U-Boot

Start with petalinux-config -c u-boot

Changes:

• MAC from eeprom together with uboot and device tree settings:
  
  • CONFIG_ENV_OVERWRITE=y
  • CONFIG_ZYNQ_MAC_IN_EEPROM is not setNVMEM=y
  • CONFIG_NET_RANDOM_ETHADDR is not setDM_RTC=y    (needed for nvmem driver because of bug in uboot)
• Boot Modes:
  • CONFIG_QSPI_BOOT=y
  • CONFIG_SD_BOOT=y
  • CONFIG_ENV_IS_IN_FAT is not set
  • CONFIG_ENV_IS_IN_NAND is not set
  • CONFIG_ENV_IS_IN_SPI_FLASH is not setCONFIG_SYS_REDUNDAND_ENVIRONMENT is not set
  • CONFIG_BOOT_SCRIPT_OFFSET=0x2A400000x3A40000
• Identification
  • CONFIG_IDENT_STRING=" TE0808_TEBF0808"

Change platform-top.h:

#no changes

Device Tree

/include/ "system-conf.dtsi"


/*------------------ gtr --------------------*/

//https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
 
/ {
  refclk3:psgtr_dp_clock {
          compatible = "fixed-clock";
          #clock-cells = <0x00>;
          clock-frequency = <27000000>;
  };

  refclk2:psgtr_pcie_usb_clock {
          compatible = "fixed-clock";
          #clock-cells = <0x00>;
          clock-frequency = <100000000>;
  };

  refclk2refclk1:psgtr_pcie_usbsata_clock {
           compatible = "fixed-clock";
           #clock-cells = <0x00>;
           clock-frequency = <100000000><150000000>;
   };
    
  refclk1//refclk0:psgtr_sataunused_clock {
  //        compatible = "fixed-clock";
  //        #clock-cells = <0x00>;
  //        clock-frequency = <150000000><100000000>;
  //};
};

&psgtr {
  clocks 
=  //refclk0:psgtr_unused_clock {<&refclk1 &refclk2 &refclk3>;
  //* ref clk instances used per lane */
  compatibleclock-names = "fixed-clockref1\0ref2\0ref3";
};



/*-------------------- SD0  // eMMC ----------------*/
&sdhci0 {
    //   #clock-cells = <0x00>;bus-width
  //        clock-frequencybus-width = <100000000><8>;
  //};
};
 
&psgtr
/*-------------------- SD1 SD2.0 ----------------*/
&sdhci1 {
  clocks = <&refclk1 &refclk2 &refclk3>// disable-wp;
  /* ref clk instances used per lane */
  clock-names = "ref1\0ref2\0ref3" no-1-8-v;
};
 
 
 
/*------------------- SDUSB --------------------*/
&sdhci0dwc3_0 {
    // disable-wpstatus = "okay";
    dr_mode  no-1-8-v;
 
};
 
&sdhci1 {= "host";
    //snps,usb3_lpm_capable;
    //snps,dis_u3_susphy_quirk;
    //snps,dis_u2_susphy_quirk;
    // disable-wpphy-names = "usb2-phy","usb3-phy";
    no-1-8-v;
 //maximum-speed = "super-speed";
};
 
 
/*------------------- ETH USBPHY --------------------*/
&dwc3_0gem3 {
    status = "okay"/delete-property/ local-mac-address;
    dr_modephy-handle = "host";
    snps,usb3_lpm_capable;
    snps,dis_u3_susphy_quirk;
    snps,dis_u2_susphy_quirk;
    phy-names = "usb2-phy","usb3-phy";
    maximum-speed = "super-speed"<&phy0>;

    nvmem-cells = <&eth0_addr>;
    nvmem-cell-names = "mac-address";

    phy0: phy0@1 {
        device_type = "ethernet-phy";
        reg = <1>;
    };
};

 
/*------------------ ETHSATA PHY --------------------*/
&gem3sata {

    /delete-property/ local-mac-address;
 ceva,p0-burst-params = <0x13084a06>;
     phy-handleceva,p0-cominit-params = <&phy0><0x18401828>;
    
    nvmem-cells ceva,p0-comwake-params = <&eth0_addr><0x614080e>;
     nvmemceva,p0-cellretry-namesparams = "mac-address"<0x96a43ffc>;
    
 ceva,p1-burst-params   phy0: phy0@1 {= <0x13084a06>;
        device_type = "ethernet-phy"ceva,p1-cominit-params = <0x18401828>;
     ceva,p1-comwake-params = <0x614080e>;
 reg = <1>;
  ceva,p1-retry-params = }<0x96a43ffc>;

};


/*-------------------- SATAQSPI PHY ---------------------*/
&sataqspi {

			ceva,p0-burst-params    num-cs = <0x13084a06><2>;
			ceva,p0-cominit-params = <0x18401828>;
			ceva,p0-comwake-params = <0x614080e>;
			ceva,p0-retry-params = <0x96a43ffc>;
			ceva,p1-burst-params = <0x13084a06>;
			ceva,p1-cominit-params = <0x18401828>;
			ceva,p1-comwake-params = <0x614080e>;
			ceva,p1-retry-params = <0x96a43ffc>;

};


/*------------------ QSPI --------------------*/ 

    flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0>, <1>;
        parallel-memories = /bits/ 64 <0x1000000 0x1000000>; /* 2* 16MB --> dummy for all types of this QSPI type */

        spi-rx-bus-width = <4>;
        spi-tx-bus-width = <4>;
        // for variants populated with n25qu512
        spi-max-frequency = <108000000>; // max. frequency also depends on the QSPI chip
                  
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0:// flash@0here {
108MHz for N25Q512A (Fast Read Quad IO STR, compatible8 =Dummy "jedec,spi-nor";
  Cycles, quad SPI protocol)
      reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;        
    };
};


/*------------------ I2C --------------------*/
&i2c0 {
    i2cswitch@73 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x73>;
        i2c-mux-idle-disconnect;
        i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
            reg = <0>;
        };
        i2c@1 { // SFP TEBF0808 PCF8574DWR
            reg = <1>;
        };
        i2c@2 { // PCIe
            reg = <2>;
        };
        i2c@3 { // SFP1 TEBF0808
            reg = <3>;
        };
        i2c@4 {// SFP2 TEBF0808
            reg = <4>;
        };
        i2c@5 { // TEBF0808 EEPROM
            reg = <5>;
            eeprom: eeprom@50 {
                compatible = "microchip,24aa025", "atmel,24c02";
                reg = <0x50>;
                
                #address-cells = <1>;
                #size-cells = <1>;
                eth0_addr: eth-mac-addr@FA {
                  reg = <0xFA 0x06>;
                };
            };
        };
        i2c@6 { // TEBF0808 FMC
            reg = <6>;
        };
        i2c@7 { // TEBF0808 USB HUB
            reg = <7>;
        };
    };
    i2cswitch@77 { // u
        compatible = "nxp,pca9548";
        reg = <0x77>;
        i2c-mux-idle-disconnect;
        i2c@0 { // TEBF0808 PMOD P1
            reg = <0>;
        };
        i2c@1 { // i2c Audio Codec
            reg = <1>;
            /*
            adau1761: adau1761@38 {
                compatible = "adi,adau1761";
                reg = <0x38>;
            };
            */
        };
        i2c@2 { // TEBF0808 Firefly A
            reg = <2>;
        };
        i2c@3 { // TEBF0808 Firefly B
            reg = <3>;
        };
        i2c@4 { //Module PLL Si5338 or SI5345
            reg = <4>;
        };
        i2c@5 { //TEBF0808 CPLD
            reg = <5>;
        };
        i2c@6 { //TEBF0808 Firefly PCF8574DWR
            reg = <6>;
        };
        i2c@7 { // TEBF0808 PMOD P3
            reg = <7>;
        };
    };
};

Kernel

Start with petalinux-config -c kernel

Changes:

• Only needed to fix JTAG Debug issue:
  
  • CONFIG_CPU_FREQ is not set
• Support PCIe memory card
  • CONFIG_NVME_CORE=yCONFIG_BLK_DEV_NVME=y=y
  • CONFIG_BLK_DEV_NVME=y
  • # CONFIG_NVME_MULTIPATH is not set
  • # CONFIG_NVME_VERBOSE_ERRORS is not set
  • # CONFIG_NVME_MULTIPATH HWMON is not set
  • # CONFIG_NVME_HWMON AUTH is not set
  • CONFIG_NVME_TARGET=y
  • # CONFIG_NVME_TARGET_PASSTHRU is not set
  • # CONFIG_NVME_TARGET_LOOP is not set
  • # CONFIG_NVME_TARGET_FC is not set
  • # CONFIG_NVME_TARGET_TCP is not set
  • # CONFIG_NVME_TARGET_AUTH is not set
  • CONFIG_SATA_AHCI=y
  • CONFIG_SATA_MOBILE_LPM_POLICY=0

Rootfs

Start with petalinux-config -c rootfs

Changes:

• • =y
  • CONFIG_SATA_MOBILE_LPM_POLICY=0

Rootfs

Start with petalinux-config -c rootfs

Changes:

• For web server app:
  • CONFIG_busybox-httpd=y
• For additional test tools only:
  • CONFIG_i2c-tools=y
  • CONFIG_packagegroup-petalinux-utils=y    (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
• For auto login:
  • CONFIG_imagefeature-serial-autologin-root=y

FSBL patch (alternative for vitis fsbl trenz patch)

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"

Boot.scr patch

Petalinux template with Trenz debug log prints, see "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\u-boot

"

Applications

See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application suitable for ZynqMP access. Need busybox-httpd

Additional Software

SI5345

File location "<project folder>/misc/PLL/Si5345_B*/Si5345-*.slabtimeproj"

General documentation how you work with these project will be available on Si5345

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.