When the configuration process successfully completes, the FPGA either actively drives the DONE pin High (DriveDone) or allows the DONE pin to float High using either an internal or external pull-up resistor, controlled by the DonePin bitstream generator option. To have DONE LED D1 lit after successful FPGA configuration, DriveDone and DonePin bitstream generator options for the DONE pin have to be set to have DONE actively driving its line (see the figure and table below).
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For the pull-up resistor value, see AR# 35002: Spartan-6 - Pull-up resistor value on INIT_B and DONE |
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DriveDone defines whether the DONE pin is an active driver or an open-drain output.
DonePin defines whether or not the DONE pin has an internal pull-up resistor.
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See Xilinx UG332: Spartan-3 Generation Configuration User Guide (paragraph "DONE Pin") for additional information on these signals.
This options are set graphically in Xilinx ISE Software Project Navigator by selecting the following:
Generate Programming File > Process Properties > Startup Options > Drive Done Pin High > check the box
Generate Programming File > Process Properties > Configuration Options > Configuration Pin Done > float
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Consult ISE Help about the Process Properties of the Generate Programming File process in the Processes pane for additional information on these properties.
All signals entering and exiting a Xilinx Spartan-3 generation FPGA must pass through the I/O resources, known as I/O blocks or IOBs. Users can specify the configuration for any unused IOB pins. This is the serial data outputs for all JTAG instruction and data registers.
This options are set graphically in Xilinx ISE Software Project Navigator by selecting the following:
Generate Programming File > Process Properties > Configuration Options > Unused IOB Pins
Select an option from the drop-down list.
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All unused I/O pins and input-only pins have a pull-down resistor to GND.In SPI Flash mode, the FPGA's internal oscillator generates the configuration clock frequency. The FPGA provides this clock on its CCLK output pin, driving the PROM's Slave Clock input pin. The FPGA begins configuring using its lowest frequency setting. If so specified in the configuration bitstream, the FPGA increases the CCLK frequency to the specified setting for the remainder of the configuration process. The maximum frequency is specified using the ConfigRate bitstream generator option. The maximum frequency supported by the FPGA configuration logic depends on the timing for the SPI Flash device. For TE0320 SPI Flash PROM, use ConfigRate = 12 or lower. For the other ones?
This options are set graphically in Xilinx ISE Software Project Navigator by selecting the following:
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