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Table of Contents |
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The Trenz Electronic TE0716 is a commercial-grade* SoM (System on Module) based on Xilinx Zynq-7000 SoC XC7Z020*, with 1GB of DDR3L-1600 SDRAM*, 32MB of SPI flash memory, 10x 12-Bit Low Power SAR ADCs, 512Kb Serial EEPROM, Gigabit Ethernet PHY transceiver, an USB PHY transceiver, a single chip USB 2.0 to UART/JTAG Interface (Xilinx License included), and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os are provided via rugged high-speed board-to-board connectors.
Refer to http://trenz.org/te0716-info for the current online version of this manual and other available documentation.
Notes: * standard values but depends on assembly version. Additional assembly options are available for cost or performance optimization upon request.
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- SoC/FPGA
- Package: CLG484
- Device: Xilinx Z-7020
- Speed: -1 *
- Temperature: C grade *.
- RAM/Storage
- Low Power DDR3 SDRAM on PS
- Data width: 32bit
- Size: def. 1GB *
- Speed: 1600 Mbps **
- QSPI boot Flash
- Data width: 4bit
- size: 32MB *
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48).
- 512Kb user MAC address serial EEPROM.
- On Board
- 10x 12-Bit Low Power SAR ADCs up to 2 MSPS (NCD98011).
- Low Power Oscillators.
- Gigabit Ethernet PHY transceiver (Marvell Alaska 88E1512).
- High-Speed USB 2.0 ULPI transceiver with full OTG support (Microchip USB3320C).
- Single chip High-Speed USB 2.0 to UART/JTAG Interface (Xilinx License included) (FTDI FT2232H).
- 2xUser RGB 2x User RGB LEDs (Green), LED FPGA "Done" (Green).
- 2 x Tactile 2x Tactile Switches (User), 1 x Tactile Switche (Reset).
- Interface
- 120 x 120x HR PL I/Os (3 banks).
- 2x PS MIOs (shared with UART TX/RX ZYNQ-FTDI).
- 1 Gbps RGMII Ethernet interface.
- High Speed USB 2.0 ULPI with full OTG support.
- High Speed USB 2.0 to UART/JTAG interface, including microUSB-B connector.
- microSD™
- JTAG
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Main Components
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| title | Initial delivery state of programmable devices on the module |
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Storage device name | IC Designator | Content | Notes |
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Quad SPI Flash | U7 | Empty | - | | 512Kb Serial EEPROM | U21 | Empty | - | | 2Kb 24AA025E48 EEPROM | U24 | Pre-programmed globally unique, 48-bit node address (MAC). | - | | 4Kb M93C66-R EEPROM | U40 | Xilinx JTAG Programmer License- | For FTDI IC only (U39). |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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JTAG Signal | B2B Connector | Notes |
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| TMS | JP2-7 | 3.3V Voltage level. Also Connected to U39 (FTDI) | | TDI | JP2-11 | 3.3V Voltage level. Also Connected to U39 (FTDI) | | TDO | JP2-10 | 3.3V Voltage level. Also Connected to U39 (FTDI) | | TCK | JP2-8 | 3.3V Voltage level. Also Connected to U39 (FTDI) | | VREF_JTAG | JP2-5 | Module Vout |
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UART Interface
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USB Signal | B2B Connector | Notes |
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xxxxxxxxxxxxxxx3.3V Voltage level.
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ETH Interface
The TE0716 provides ETH access to the TE0716 SoM through B2B connector JP1. The ETH interface is connected later to the Zynq Ethernet PS (Ethernet 0), by using a ETH PHY.
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ETH Signal | B2B Connector | Notes |
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xx |
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PHY_MDI0_P PHY_MDI0_ N | JP1-5 JP1- |
xxx | PHY_MDI1_P PHY_MDI1_ N | JP1-7 JP1- |
xxxPHY_MDI2_P PHY_MDI2_ N | JP1-68 JP1- |
xxx | PHY_MDI3_P PHY_MDI3_ N | JP1- |
x3.3V Voltage level. | xxx
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ADC Interface
The analog inputs of the ADCs are connected to B2B connector JP1.
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ADC Signal | B2B Connector | Notes |
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ADC0_P
ADC0_N | JP1-106..107 | SAR ADC, U1.
3.3V Max. Voltage on any pin. | ADC1_P
ADC1_N | JP1-46..47 | SAR ADC, U3.
3.3V Max. Voltage on any pin. | ADC2_P
ADC2_N | JP1-109..110 | SAR ADC, U10.
3.3V Max. Voltage on any pin. | ADC3_P
ADC3_N | JP1-49..50 | SAR ADC, U15.
3.3V Max. Voltage on any pin. | ADC4_P
ADC4_N | JP1-112..113 | SAR ADC, U17.
3.3V Max. Voltage on any pin. | ADC5_P
ADC5_N | JP1-52..53 | SAR ADC, U2.
3.3V Max. Voltage on any pin. | ADC6_P
ADC6_N | JP1-115..116 | SAR ADC, U4.
3.3V Max. Voltage on any pin. | ADC7_P
ADC7_N | JP1-55..56 | SAR ADC, U11.
3.3V Max. Voltage on any pin. | ADC8_P
ADC8_N | JP1-118..119 | SAR ADC, U16.
3.3V Max. Voltage on any pin. | ADC9_P
ADC9_N | JP1-58..59 | SAR ADC, U19.
3.3V Max. Voltage on any pin. |
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PWM Interface
@Guillermo: Hier die JP2 Stecker Pins wo PWN rausgeführt wird
Micro USB -JTAG/UART
A microUSB-B connector (J13) is connected to the FTDI. It provides the ability to communicate to the PL FPGA via JTAG, as well as to the PS UART (UART 0).
Caution: because the TE0716 also provides UART and JTAG access to the FPGA through B2B connectors JP1 and JP2 respectively, ONLY ONE connection for UART, and ONLY ONE connection for JTAG, should be used at the time! (please read "UART Interface" and "JTAG Interface" above in the "Board to Board (B2B)" Section).
Micro SD Socket
A microSD™ card connector (J2) is connected via U35 (SD/SDIO Multiplexer - Level Translator) to Zynq PS (Bank501/SDIO 0). It is a Push-On/Push-Off socket type, and work with a voltage level of 3.3V.
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The PWM signals are connected to B2B connector JP2. All this digital signals are connected to PL Bank 33 (except for PWM_6_H and PWM_6_L which are connected to PL Bank 13). These signals could be also used as normal single ended I/Os.
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PWM Signal | B2B Connector | Notes |
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| PWM_0_H | JP2-103 | 3.3V Max. Voltage on any pin. | | PWM_0_L | JP2-104 | 3.3V Max. Voltage on any pin. | | PWM_1_H | JP243 | 3.3V Max. Voltage on any pin. | | PWM_1_L | JP2-44 | 3.3V Max. Voltage on any pin. | | PWM_10_H | JP2-118 | 3.3V Max. Voltage on any pin. | | PWM_10_L | JP2-119 | 3.3V Max. Voltage on any pin. | | PWM_11_H | JP2-58 | 3.3V Max. Voltage on any pin. | | PWM_11_L | JP2-59 | 3.3V Max. Voltage on any pin. | | PWM_2_H | JP2-106 | 3.3V Max. Voltage on any pin. | | PWM_2_L | JP2-107 | 3.3V Max. Voltage on any pin. | | PWM_3_H | JP2-46 | 3.3V Max. Voltage on any pin. | | PWM_3_L | JP2-47 | 3.3V Max. Voltage on any pin. | | PWM_4_H | JP2-109 | 3.3V Max. Voltage on any pin. | | PWM_4_L | JP2-110 | 3.3V Max. Voltage on any pin. | | PWM_5_H | JP2-49 | 3.3V Max. Voltage on any pin. | | PWM_5_L | JP2-50 | 3.3V Max. Voltage on any pin. | | PWM_6_H | JP2-112 | 3.3V Max. Voltage on any pin. | | PWM_6_L | JP2-113 | 3.3V Max. Voltage on any pin. | | PWM_7_H | JP2-52 | 3.3V Max. Voltage on any pin. | | PWM_7_L | JP2-53 | 3.3V Max. Voltage on any pin. | | PWM_8_H | JP2-115 | 3.3V Max. Voltage on any pin. | | PWM_8_L | JP2-116 | 3.3V Max. Voltage on any pin. | | PWM_9_H | JP2-55 | 3.3V Max. Voltage on any pin. | | PWM_9_L | JP2-56 | 3.3V Max. Voltage on any pin. |
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Micro USB -JTAG/UART
A microUSB-B connector (J13) is connected to the FTDI. It provides the ability to communicate to the PL FPGA via JTAG, as well as to the PS UART (UART 0).
Caution: because the TE0716 also provides UART and JTAG access to the FPGA through B2B connectors JP1 and JP2 respectively, ONLY ONE connection for UART, and ONLY ONE connection for JTAG, should be used at the time! (please read "UART Interface" and "JTAG Interface" above in the "Board to Board (B2B)" Section).
Micro SD Socket
A microSD™ card connector (J2) is connected via U35 (SD/SDIO Multiplexer - Level Translator) to Zynq PS (Bank501/SDIO 0). It is a Push-On/Push-Off socket type, and work with a voltage level of 3.3V.
MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: | MIO Pin | Connected to | B2B | Notes |
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| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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PS MIO banks 500/501 signal connections to interface.
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| MIO Pin | Connected to | B2B | Notes |
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| 1..6 | SPI-CS , SPI-DQ0... SPI-DQ3 SPI-SCK | - | QSPI Flash, U7 | | 11..13 | LED1_R..G..B | - | LED D4 | | 14, 15 | UART_RX_ZYNQ, UART_TX_ZYNQ | JP1 | 3.3V Voltage level. Also Connected to U36-2. To use this signal from B2B connector, "UART_OB_DISABLE" (JP1-11) must be "High". | | 16..27 | ETH-TXCK, ETH-TXD0..ETH-TXD3, ETH-TXCTL, ETH-RXCK, ETH-RXD0..ETH-RXD3, ETH-RXCTL | - | Gigabit ETH Transceiver, U8 | | 28..39 | OTG-DATA0..OTG-DATA7, OTG-DIR, OTG-STP, OTG-NXT, OTG-CLK | - | USB 2.0 ULPI transceiver, U18 | | 40..45 | PS_SD_CLK, PS_SD_CMD, PS_SD_DAT0..PS_SD_DAT3 | J2 | 3.3V Voltage level. Connected to PS via U35 (SD/SDIO Multiplexer - Level Translator) | | 46, 47 | I2C_SCL, I2C_SDA | - | General Purpose EEPROM, U21
MAC EEPROM, U24 | | 51 | PHY-RST | - | Gigabit ETH Transceiver, U8
USB 2.0 ULPI transceiver, U18 | | 52, 53 | ETH-MDC, ETH-MDIO | - | Gigabit ETH Transceiver, U8 |
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Test Points
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the SchematicTest Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: | Test Point | Signal | MIO Pin | Connected to | B2B | Notes |
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| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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| MIO Pin | Connected to | B2B | Notes |
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| 1..6 | SPI-CS , SPI-DQ0... SPI-DQ3 SPI-SCK | - | QSPI Flash, U7 |
| 11..13 | LED1_R..G..B | - | LED D4 |
| 14, 15 | UART_RX_ZYNQ, UART_TX_ZYNQ | JP1 | 3.3V Voltage level. Also Connected to U36-2. To use this signal from B2B connector, "UART_OB_DISABLE" (JP1-11) must be "High". |
| 16..27 | ETH-TXCK, ETH-TXD0..ETH-TXD3, ETH-TXCTL, ETH-RXCK, ETH-RXD0..ETH-RXD3, ETH-RXCTL | - | Gigabit ETH Transceiver, U8 |
| 28..39 | OTG-DATA0..OTG-DATA7, OTG-DIR, OTG-STP, OTG-NXT, OTG-CLK | - | USB 2.0 ULPI transceiver, U18 |
| 40..45 | PS_SD_CLK, PS_SD_CMD, PS_SD_DAT0..PS_SD_DAT3 | J2 | 3.3V Voltage level. Connected to PS via U35 (SD/SDIO Multiplexer - Level Translator) |
| 46, 47 | I2C_SCL, I2C_SDA | - | General Purpose EEPROM, U21
MAC EEPROM, U24 |
| 51 | PHY-RST | - | Gigabit ETH Transceiver, U8
USB 2.0 ULPI transceiver, U18 |
| 52, 53 | ETH-MDC, ETH-MDIO | - | Gigabit ETH Transceiver, U8 |
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| Test Point | Signal | Connected to | Notes |
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| TP1 | +1.0V | U37, DC-DC Converter
| PL-VCCINT | | TP2 | ADC_VAA | U38, LDO Regulator
| ADC_VAA Analog supply/reference, (3.3V) | | TP3 | +1.5V | U43, DC-DC Converter | - | | TP4 | +1.8V | U45, DC-DC Converter | - | | TP5 | VTT | U47, DDR Termination Regulator | (0.75V) | | TP6 | VTTREF | U47, DDR Termination Regulator | (0.75V) | | TP7 | +5.0V | JP1-(1,2,3)
JP2-(1,2,3) | Main Digital Power Input | | TP8 | +3.3V | U46, DC-DC Converter | - | | TP9 | +5.0V_VAA | JP1-(43,44) | Main Analog Low Power Input | | TP10 | +3.3V_ADC | U23, LDO Regulator | ADC's Digital I/O supply | | TP11 | GND | - | - | | TP12 | GND | - | - | | TP13 | SPI-DQ3/M0 | MIO_5 | Remove SD card and short with TP14 for JTAG only mode | | TP14 | GND | - | - |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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| you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.
Example:
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10 | PWR_PL_OK | J2-120 | Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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| Test Point | Signal | Connected to | Notes |
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| TP1 | +1.0V | U37, DC-DC Converter
| PL-VCCINT |
| TP2 | ADC_VAA | U38, LDO Regulator
| ADC_VAA Analog supply/reference, (3.3V) |
| TP3 | +1.5V | U43, DC-DC Converter | - |
| TP4 | +1.8V | U45, DC-DC Converter | - |
| TP5 | VTT | U47, DDR Termination Regulator | (0.75V) |
| TP6 | VTTREF | U47, DDR Termination Regulator | (0.75V) |
| TP7 | +5.0V | JP1-(1,2,3)
JP2-(1,2,3) | Main Digital Power Input |
| TP8 | +3.3V | U46, DC-DC Converter | - |
| TP9 | +5.0V_VAA | JP1-(43,44) | Main Analog Low Power Input |
| TP10 | +3.3V_ADC | U23, LDO Regulator | ADC's Digital I/O supply |
| TP11 | GND | - | - |
| TP12 | GND | - | - |
| TP13 | SPI-DQ3/M0 | MIO_5 | Remove SD card and short with TP14 for JTAG only mode |
| TP14 | GND | - | - |
On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes :
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| Chip/Interface | Designator | Notes |
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| DDR3 SDRAM | U12, U13 | - | | Quad SPI Flash | U7 | - | | MAC EEPROM | U24 | - | | General Purpose EEPROM | U21 | - | | SAR ADCs | U1, U2, U3, U4, U10, U11, U15, U16, U17, U19 | - | | Clock Sources | U6, U9, U14, U41 | - | | Gigabit Ethernet PHY | U8 | - | | USB 2.0 ULPI transceiver | U18 | - | | FTDI USB 2.0 to UART/JTAG | U39 | - | | LEDs | D3, D4, D5 | - | | Switches | S1, S2, S3 | - |
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DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE0716 module has two 500MByte DDR3L SDRAM chips (U12 & U13) fully connected to PS DDR BANK 502, and arranged into 32-bit wide memory bus providing total on-board memory size of 1GByte.
- Configuration: 256Mx16*
- Supply voltage: 1.35V (1.5V tolerant).
- Speed: 1.25ns @ CL11 (DDR3-1600)*
- Temperature: Industrial Range -40°C to +95°C Tcase.
Notes: * standard value but depends on assembly version.
Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
On-board 32MByte QSPI flash memory S25FL256S (U7) could be used to store the initial FPGA configuration file. After configuration completes, the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
- Part number: S25FL256SAGBHI20*
- Supply voltage: 3.3V (2.7V - 3.6V).
- Speed: 133MHz max.*
- Temperature: Industrial Range -40°C to +85°C.
Notes: * standard number/value but depends on assembly version.
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| title | On board peripheralsQuad SPI interface MIOs and pins |
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| Chip/Interface | Designator | Notes |
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| DDR3 SDRAM | U12, U13 | - |
| Quad SPI Flash | U7 | - |
| MAC EEPROM | U24 | - |
| General Purpose EEPROM | U21 | - |
| SAR ADCs | U1, U2, U3, U4, U10, U11, U15, U16, U17, U19 | - |
| Clock Sources | U6, U9, U14, U41 | - |
| Gigabit Ethernet PHY | U8 | - |
| USB 2.0 ULPI transceiver | U18 | - |
| FTDI USB 2.0 to UART/JTAG | U39 | - |
| LEDs | D3, D4, D5 | - |
| Switches | S1, S2, S3 | - |
DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE0716 module has two 500MByte DDR3L SDRAM chips (U12 & U13) fully connected to PS DDR BANK 502, and arranged into 32-bit wide memory bus providing total on-board memory size of 1GByte.
| MIO Pin | Schematic | U7 Pin | Notes |
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| MIO1 | SPI-CS | CS# | - | | MIO3 | SPI-DQ1/M1 | SO/IO1 | - | | MIO4 | SPI-DQ2/M2 | WP#/IO2 | - | | MIO2 | SPI-DQ3/M3 | HOLD#/IO3 | - | | MIO5 | SPI-DQO/M0 | SI/IO0 | - | | MIO6 | SPI-SCK/M4 | SCK | - |
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EEPROM
There are 2x EEPROMs sharing the same I2C bus (I2C interface is connected to the Zynq I2C PS (I2C 0).:
MAC-Address EEPROM
A 2Kbit 24AA025E48 serial EEPROM I2C memory (U24), connected to the BANK501 PSMIOs, contains a globally unique 48-bit node address, which is compatible with EUI-48TM specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks, the upper half of the array (80h-FFh), stores the 48-bit node address and is permanently write-protected, while the other block is available for application use.
- Part number: 24AA025E48T-I/OT
- Supply voltage: 1.8V (1.7V - 5.5V).
- FCLK: 100KHz (@VCC=1.8V)
- Configuration: 256Mx16*
- Supply voltage: 1.35V (1.5V tolerant).
- Speed: 1.25ns @ CL11 (DDR3-1600)*
- Temperature: Industrial Range -40°C to +95°C Tcase.
Notes: * standard value but depends on assembly version.
Quad SPI Flash Memory
| Page properties |
|---|
|
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
General Purpose EEPROM
The TE0716 module has also a 512Kb Serial EEPROM I2C memory (U21)On-board 32MByte QSPI flash memory S25FL256S (U7) could be used to store the initial FPGA configuration file. After configuration completes, the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
- Part number: S25FL256SAGBHI20CAT24C512WI-GT3
- Supply voltage: 31.3V 8V (21.7V 8V - 35.6V5V).Speed: 133MHz max.
- FCLK: 100KHz/400KHz/1MHz
- Temperature: Industrial Range -40°C to +85°C.
...
| Scroll Title |
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| anchor | Table_OBP_SPIEEP |
|---|
| title | Quad SPI I2C EEPROM interface MIOs and pins |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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|
U7 | MIO1 | SPI-CS | CS# | - | | MIO3 | SPI-DQ1/M1 | SO/IO1 | - | | MIO4 | SPI-DQ2/M2 | WP#/IO2 | - | | MIO2 | SPI-DQ3/M3 | HOLD#/IO3 | - | | MIO5 | SPI-DQO/M0 | SI/IO0 | - | | MIO6 | SPI-SCK/M4 | SCK | - | |
EEPROM
There are 2x EEPROMs sharing the same I2C bus (I2C interface is connected to the Zynq I2C PS (I2C 0).:
MAC-Address EEPROM
A 2Kbit 24AA025E48 serial EEPROM I2C memory (U24), connected to the BANK501 PSMIOs, contains a globally unique 48-bit node address, which is compatible with EUI-48TM specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks, the upper half of the array (80h-FFh), stores the 48-bit node address and is permanently write-protected, while the other block is available for application use.
- Part number: 24AA025E48T-I/OT
- Supply voltage: 1.8V (1.7V - 5.5V).
- FCLK: 100KHz (@VCC=1.8V)
- Temperature: Industrial Range -40°C to +85°C.
General Purpose EEPROM
The TE0716 module has also a 512Kb Serial EEPROM I2C memory (U21).
...
|
|---|
| MIO46 | I2C_SCL | SCL | - | | MIO47 | I2C_SDA | SDA | - |
|
| Scroll Title |
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| anchor | Table_OBP_I2C_EEPROM |
|---|
| title | I2C address for EEPROM |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
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| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
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| style | |
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| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| I2C Device | I2C Address | Designator | Notes |
|---|
| 2K Serial EEPROMs with EUI-48™ | 0x53 (7bit) | U24 | - | | 512Kb Serial EEPROM | 0x50 (7bit) | U21 | - |
|
ADCs
The TE0716 module has 10x 12-Bit Low Power SAR Analog-to-Digital Converter, fully differential input, signed output, with SPI−compatible interface (NCD98011), which are connected to the FPGA PL BANK34.
- Part number: NCD98011XMXTAG
- Analog supply and ADC reference voltage (VCC): 3.3V (1.65V – 3.6V).
- Digital I/O supply voltage (VDD): 3.3V (1.65V – 3.6V).
- Differential analog inputs: 1 per ADC.
- Full−Scale Analog Input Voltage Span: +VCC max Vppd, -VCC min Vppd, (VCM to VCC/2).
- Absolute Voltage Range Vinp or Vinn to GND: VCC + 0.1V
- Sampling rate: 2 MSPS max.
- SNR: 70dB @1KHz fIN.
- THD: -80dB @1KHz fIN.
- Junction Temperature: Range -40°C to +125°C.
All the analog inputs are connected to B2B JP1 as follows:
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| Scroll Title |
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| anchor | Table_OBP_EEPINADC |
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| title | I2C EEPROM ADC Analog interface MIOs and pins |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MIO PinU21/U24 PinMIO46| I2C_SCL | SCL | - | | MIO47 | I2C_SDA | SDA | - | |
| Scroll Title |
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| anchor | Table_OBP_I2C_EEPROM |
|---|
| title | I2C address for EEPROM |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| I2C Device | I2C Address | Designator | Notes |
|---|
| 2K Serial EEPROMs with EUI-48™ | 0xA6 (write)
0xA7 (read)
0x53 (7bit) | U24 | - |
| 512Kb Serial EEPROM | 0xA0 (write)
0xA1 (read)
0x50 (7bit) | U21 | - |
ADCs
The TE0716 module has 10x 12-Bit Low Power SAR Analog-to-Digital Converter, fully differential input, signed output, with SPI−compatible interface (NCD98011), which are connected to the FPGA PL BANK34.
- Part number: NCD98011XMXTAG
- Analog supply and ADC reference voltage (VCC): 3.3V (1.65V – 3.6V).
- Digital I/O supply voltage (VDD): 3.3V (1.65V – 3.6V).
- Differential analog inputs: 1 per ADC.
- Full−Scale Analog Input Voltage Span: +VCC max Vppd, -VCC min Vppd, (VCM to VCC/2).
- Absolute Voltage Range Vinp or Vinn to GND: VCC + 0.1V
- Sampling rate: 2 MSPS max.
- SNR: 70dB @1KHz fIN.
- THD: -80dB @1KHz fIN.
- Junction Temperature: Range -40°C to +125°C.
...
ADC0_P
ADC0_N | 106 - 107 | 3.3V Max Voltage on any pin. | | U2 | ADC5_P
ADC5_N | 52 - 53 | 3.3V Max Voltage on any pin. | | U3 | ADC1_P
ADC1_N | 46 - 47 | 3.3V Max Voltage on any pin. | | U4 | ADC6_P
ADC6_N | 115 - 116 | 3.3V Max Voltage on any pin. | | U10 | ADC2_P
ADC2_N | 109 - 110 | 3.3V Max Voltage on any pin. | | U11 | ADC7_P
ADC7_N | 55 - 56 | 3.3V Max Voltage on any pin. | | U15 | ADC3_P
ADC3_N | 49 - 50 | 3.3V Max Voltage on any pin. | | U16 | ADC8_P
ADC8_N | 118 - 119 | 3.3V Max Voltage on any pin. | | U17 | ADC4_P
ADC4_N | 112 - 113 | 3.3V Max Voltage on any pin. | | U19 | ADC9_P
ADC9_N | 58 - 59 | 3.3V Max Voltage on any pin. |
|
All the digital signals are connected to PL Bank 34 as follows:
| Scroll Title |
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| anchor | Table_OBP_INADCADC |
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| title | ADC Analog to PL interface and pins |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
|---|
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B2B JP1 pinADC0_P
ADC0_N | 106 - 107 | 3.3V Max Voltage on any pin. | | U2 | ADC5_P
ADC5_N | 52 - 53 | 3.3V Max Voltage on any pin. | U3 | ADC1_P
ADC1_N | 46 - 47 S0_CLK S0_CSN S0_OUT | J18 J16 K18 | 3.3V Max Voltage on any pin. |
U4 | ADC6_P
ADC6_N | 115 - 116 | U2 | S5_CLK S5_CSN S5_OUT | M21 T16 T17 | 3.3V Max Voltage on any pin. |
U10ADC2_P
ADC2_N | 109 - 110 | 3.3V Max Voltage on any pin. | U11 | ADC7_P
ADC7_N | 55 - 56 S1_CLK S1_CSN S1_OUT | L18 J21 L19 | 3.3V Max Voltage on any pin. |
U15 | ADC3_P
ADC3_N | 49 - 50 | | U4 | S6_CLK S6_CSN S6_OUT | J22 K21 J20 | 3.3V Max Voltage on any pin. |
U16 | ADC8_P
ADC8_N | 118 - 119 | | U10 | S2_CLK S2_CSN S2_OUT | M22 R21 R20 | 3.3V Max Voltage on any pin. |
U17 | ADC4_P
ADC4_N | 112 - 113 | U11 | S7_CLK S7_CSN S7_OUT | L22 M20 M19 | 3.3V Max Voltage on any pin. |
U19 | ADC9_P
ADC9_N | 58 - 59 | | U15 | S3_CLK S3_CSN S3_OUT | J17 J15 L17 | 3.3V Max Voltage on any pin. |
|
All the diigital signals are connected to PL Bank 34 as follows:
| U16 | S8_CLK S8_CSN S8_OUT | M17 N18 N17 | 3.3V Max Voltage on any pin. | | U17 | S4_CLK S4_CSN S4_OUT | P17 L21 P18 | 3.3V Max Voltage on any pin. | | U19 | S9_CLK S9_CSN S9_OUT | K15 P21 P20 | 3.3V Max Voltage on any pin. |
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| Scroll Title |
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| anchor | Table_OBP_ADC |
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| title | ADC interface PL and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Schematic | PL Pin | Notes |
|---|
U1 | U2 | U3 | U4 | U10 | U11 | U15 | U16 | U17 | U19
Clock Sources
The TE0716 board is equipped with 4x Oscillators, every one with its specific function.
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| Scroll Title |
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| anchor | Table_OBP_ETH |
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| title | Ethernet PHY to Zynq SoC connections |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
|---|
| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| U8 Pin | Signal Name | Connected to | Signal Description | Note |
|---|
TX_CLK | ETH-TXCK | MIO16 | RGMII Transmit Clock | - | TXD[0..3] | ETH-TXD0..3 | MIO17..20 | RGMII Transmit Data
| - | TX_CTRL | ETH-TXCTL | MIO21 | RGMII Transmit Control | - | RX_CLK | ETH-RXCK | MIO22 | RGMII Receive Clock | - | RXD[0..3] | ETH-RXD0..3 | MIO23..26 | RGMII Receive Data | - | RX_CTRL | ETH-RXCTL | MIO27 | RGMII Receive Control | - | MDC | ETH-MDC | MIO52 | Management data clock reference | - | MDIO | ETH-MDIO | MIO53 | Management data | - | RESETn | PHY-RST | MIO51, U18 | Hardware reset. Active low. | Shared with U18 (RESETB) USB | MDIP[0..3] MDIN[0..3] | PHY_MDI0..3_P
PHY_MDI0..3_N | JP1 | Media Dependent Interface | - | XTAL_IN | ETH-CLK | U9 | Reference Clock Input | see also Clock Sources section | LED[0..1] | PHY_LED0..1 | FPGA BANK 33 | LED output | - |
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...
| Scroll Title |
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| anchor | Table_OBP_USB |
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| title | USB PHY to Zynq SoC connections |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
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| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
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| style | |
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| widths | |
|---|
| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| U18 Pin | Signal Name | Connected to | Signal Description | Note |
|---|
CLKOUT | OTG-CLK | MIO36 | ULPI Output Clock | - | DATA[0..3] | OTG-DATA0..3 | MIO32..35 | ULPI bi-directional data bus | - | DATA[4] | OTG-DATA4 | MIO28 | ULPI bi-directional data bus | - | DATA[5..7] | OTG-DATA5..7 | MIO37..39 | ULPI bi-directional data bus | - | DIR | OTG-DIR | MIO29 | Controls the direction of the data bus | - | STP | OTG-STP | MIO30 | terminates transfers PHY input | - | NXT | OTG-NXT | MIO31 | control data flow into and out of the PHY | - | RESETB | PHY-RST | MIO51, U8 | reset and suspend the PHY. Active low. | Shared with U8 (RESETn) Ethernet | DP | USB_OTG_D_P | JP2-64 | D+ pin of the USB cable | 3.3V Voltage level | DM | USB_OTG_D_N | JP2-65 | D- pin of the USB cable | 3.3V Voltage level | ID | USB_OTG_ID | JP2-66 | ID pin of the USB cable | 3.3V Voltage level | CPEN | USB_VBUS_EN | JP2-67 | Controls the external VBUS power switch | 3.3V Voltage level | VBUS | USB_VBUS | JP2-68 | For RVBUS connection | Max. voltage: 5.5V | REFCLK | OTG-RCLK | U14 | ULPI clock input | see also Clock Sources section |
|
...
| Scroll Title |
|---|
| anchor | Table_OBP_FTDI |
|---|
| title | USB FTDI to Zynq SoC connections |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
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| style | |
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| widths | |
|---|
| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| U39 Pin | Signal Name | Connected to | Signal Description | Note |
|---|
| DP | D_JTAG_P | J13-2 | USB Data Signal Plus | 3.3V Voltage level | | DM | D_JTAG_N | J13-3 | USB Data Signal Minus | 3.3V Voltage level | | ADBUS0 | TCK | JP2-8,
TCK_0 (FPGA PL BANK 0) | Clock Signal Output | 3.3V Voltage level.
MPSSE Mode | | ADBUS1 | TDI | JP2-11,
TDI_0 (FPGA PL BANK 0) | Serial Data Output | 3.3V Voltage level.
MPSSE Mode | | ADBUS2 | TDO | JP2-10,
TDO_0 (FPGA PL BANK 0) | Serial Data Input | 3.3V Voltage level.
MPSSE Mode | | ADBUS3 | TMS | JP2-7,
TMS_0 (FPGA PL BANK 0) | Output Signal Select | 3.3V Voltage level.
MPSSE Mode | | BDBUS0 | UART_TX_OB | U36-5 | Asynchronous serial TXD | U36-3 Bus Switch pin connects later this signal to UART_RX_ZYNQ when UART_OB_DISABLE is low or floating. | | BDBUS1 | UART_RX_OB | U36-6 | Asynchronous serial RXD | U36-2 Bus Switch pin connects later this signal to UART_TX_ZYNQ when UART_OB_DISABLE is low or floating. | | OSCI | OSCI |
| Oscillator input | - | | EECS, EECLK, EEDATA | EECS, EECLK, EEDATA | U40-1..3 | EEPROM interface | - | | - | UART_OB_DISABLE | JP1-11 | Enable signal of the FTDI-PS_UART Bus Switch U36. | Active Low!. |
|
...
Power supply with minimum current capability of 3.0 A (TBD*) for system startup is recommended.
...
* TBD - To Be Determined
Power Consumption
| Scroll Title |
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| anchor | Table_PWR_PC |
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| title | Power Consumption |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Input Pin | Typical Current |
|---|
| +5.0V | TBD* | | +5.0V_VAA | less than 250mA (TBD*) |
|
* TBD - To Be Determined
Power Distribution Dependencies
| Scroll Title |
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| anchor | TableFigure_PWR_PCPD |
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| title | Power ConsumptionDistribution |
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tablelayoutorientationportrait |
| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
|---|
| cellHighlighting | true |
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| Power Input Pin | Typical Current |
|---|
| +5.0V | TBD* |
| +5.0V_VAA | less than 250mA (TBD) |
* TBD - To Be Determined
...
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| diagramName | PWR-PD-TE0716-01 |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramDisplayName | |
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| lbox | true |
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| diagramWidth | 643 |
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| revision | 2 |
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| Scroll Only |
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Power-On Sequence
The TE0716 has only one common "PGOOD" signal (from U37, U43, U45 and U46), and there is no Enable for the board. You could control the startup of the board IC, by controlling the +5.0V and the +5.0V_VAA input signals only.
| Scroll Title |
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| anchor | Figure_PWR_PDPS |
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| title | Power DistributionSequency |
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| Scroll Title |
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| anchor | Figure_PWR_PS |
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| title | Power Sequency |
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| Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. | draw.io Diagram |
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| border | falsetrue |
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| |
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| diagramName | PWR-PDPS-TE0716-01 |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden | diagramDisplayNametop |
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| lbox | true |
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| diagramWidth | 643641 |
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| revision | 2 |
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| Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Power-On Sequence
| Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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 Image Added
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Voltage Monitor Circuit
The TE0716 has also a Voltage Monitor IC. It keeps nRST signal low if the FPGA core voltage (+1.0V) drops under 0.84V or the 3.3V power supply drops to 2.94V or less.
Power Good signal is unique and comes from the power supplies IC U37, U43, U45 and U46, as you can see in the previous section "Power-On Sequence", and also could make nRST to remain low until PGOOD is high.
See also "Reset process." section in "Configuration Signals" for additional information.
| Scroll Title |
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| anchor | Figure_PWR_VMC |
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| title | Voltage Monitor Circuit |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| |
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| diagramName | PWR-PM-TE0716-01 |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramDisplayName | |
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| lbox | true |
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| diagramWidth | 641 |
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| revision | 3 |
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| Scroll Only |
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 Image Added
| Create DrawIO object here: Attention if you copy from other page, objects are only linked. | | Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Power Rails
| Scroll Title |
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| anchor | Table_PWR_PR |
|---|
| title | Module power rails. |
|---|
|
| Scroll Table Layout |
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| orientation | portrait |
|---|
| sortDirection | ASC |
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| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
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| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
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|
| Power Rail Name | B2B Connector JP1 Pin | B2B Connector JP2 Pin | Direction | Notes |
|---|
| +5.0V | 1, 23, 35 | 1, 23, 35 | Input | Main Supply voltage from the carrier board | | +5.0V_VAA | 43, 44 | - | Input | Analog Supply voltage from the carrier board | | +3.3V (VREF_JTAG) | - | 5 | Output | JTAG reference voltage. |
|
...
| Page properties |
|---|
|
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
| Include Page |
|---|
| PD:6 x 6 SoM LSHM B2B ConnectorsPD: |
|---|
| 6 x 6 SoM LSHM B2B Connectors |
|---|
|
|
...
| Scroll Title |
|---|
| anchor | Table_TS_AMR |
|---|
| title | PS absolute Absolute maximum ratings |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
style | widths | | sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
| | sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Symbols | Description | Min | Max | Unit | Reference |
|---|
| +5.0V | Main Supply voltage from the carrier board | -0.3 | 6.0 | V | NCV6357 Datasheet
NCV6323 Datasheet
NCP160 Datasheet | | +5.0V_VAA | Analog Supply voltage from the carrier board | -0.3 | 6.0 | V | NCP160 Datasheet | | MIO 500 | I/O input voltage for MIO bank 500 | -0.4 | 3.85 | V | Xilinx DS187 Datasheet | | MIO 501 | I/O input voltage for MIO bank 501 | -0.4 | 2.35 | V | Xilinx DS187 Datasheet | | PL HR | I/O input voltage for HR banks | -0.4 | 3.85 | V | Xilinx DS187 Datasheet | | ADCx_P/N | I/O input voltage for ADCs analog inputs | -0.3 | 3.63 | V | NCD98011 Datasheet |
| Symbols | Description | Min | Max | Unit |
|---|
V | V | V | V | V | V | V | V
|
Recommended Operating Conditions
...
| Scroll Title |
|---|
| anchor | Table_TS_ROC |
|---|
| title | Recommended operating conditions. |
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|
| Scroll Table Layout |
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| orientation | portrait |
|---|
| sortDirection | ASC |
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| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
|---|
|
| Parameter | Min | Max | Units | Reference Document |
|---|
+5.0V Main Supply input voltage
from the carrier board | 4.0 | 5.5 | V | 7WB3125 Datasheet NCV6357 Datasheet NCV6323 Datasheet NCP160 Datasheet | +5.0V_VAA Analog Supply input voltage
from the carrier board | 3.75 | 5.5 | V | NCP160 Datasheet | | I/O input voltage for MIO bank 500 | -0.2 | 3.5 | V | Xilinx DS187 Datasheet | | I/O input voltage for MIO bank 501 | -0.2 | 2.0 | V | Xilinx DS187 Datasheet | | I/O input voltage for HR banks | -0.2 | 3.5 | V | Xilinx DS187 Datasheet | | I/O input voltage for ADCs analog inputs | -0.2 | 3.4 | V | NCD98011 Datasheet | See ???? datasheets. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | V | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. | °C | See Xilinx ???? datasheet. |
|
Physical Dimensions
Module size: 45 mm × 65 mm. Please download the assembly diagram for exact numbers.
Mating height with 61982 receptacle connectors: 5mm, 7mm, 13mm and 17mm stack heights.
PCB thickness: 1.65 mm.
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| Scroll Title |
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| anchor | Figure_TS_PD |
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| title | Physical Dimension |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| |
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| diagramName | PD-TE0716-01 |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramDisplayName | |
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| lbox | true |
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| diagramWidth | 641 |
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| revision | 2 |
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| Scroll Only |
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| scroll-pdf | true |
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| scroll-office | true |
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| scroll-chm | true |
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| scroll-docbook | true |
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| scroll-eclipsehelp | true |
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| scroll-epub | true |
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| scroll-html | true |
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|  Image Modified
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Currently Offered Variants
| Scroll Title |
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| anchor | Table_VCP_SO |
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| title | Trenz Electronic Shop Overview |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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|
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| Scroll Title |
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| anchor | Table_RH_HRH |
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| title | Hardware Revision History |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Changes | Documentation LinkChanges | Documentation Link |
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| 2020-10-25 | REV01 | Initial Release | REV01 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
| Scroll Title |
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| anchor | Figure_RV_HRN |
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| title | Board hardware revision number. |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| |
|---|
| diagramName | RH-HRN-TE0716-01 |
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| simpleViewer | false |
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| width | |
|---|
| links | auto |
|---|
| tbstyle | hidden |
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| diagramDisplayName | |
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| lbox | true |
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| diagramWidth | 545 |
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| revision | 4 |
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| Scroll Only |
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 Image Added
| Create DrawIO object here: Attention if you copy from other page, objects are only linked. | | Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Document Change History
| Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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| Scroll Title |
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| anchor | Table_RH_DCH |
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| title | Document change history. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Date | Revision | Contributor | Description |
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| Page info |
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| infoType | Modified date |
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| dateFormat | yyyy-MM-dd |
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| type | Flat |
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| | Page info |
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| infoType | Current version |
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| prefix | v. |
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| type | Flat |
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| showVersions | false |
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| | Page info |
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| infoType | Modified by |
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| type | Flat |
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| showVersions | false |
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|
change list | | | 2020-10-30 | v.85 | Guillermo Herrera | | -- | all | | Page info |
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| infoType | Modified users |
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| type | Flat |
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| showVersions | false |
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...