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Scroll Title
anchorFigure_OV_BD
titleTE0716-01 block diagram


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Main Components

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Scroll Title
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titleInitial delivery state of programmable devices on the module

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Storage device name

IC Designator

Content

Notes

Quad SPI Flash

U7Empty

-

512Kb Serial EEPROMU21Empty

-

2Kb 24AA025E48 EEPROMU24Pre-programmed globally unique, 48-bit node address (MAC).-
4Kb M93C66-R EEPROMU40Xilinx JTAG Programmer License-For FTDI IC only (U39).



Configuration Signals

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idComments
  • Overview of Boot Mode, Reset, Enables.

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The PWM signals are connected to B2B connector JP2. All this digital signals are connected to PL Bank 33 (except for PWM_6_H  and PWM_6_L which are connected to PL Bank 13). This These signals could be also used as normal single ended I/Os.

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  • Part number: S25FL256SAGBHI20*
  • Supply voltage: 3.3V (2.7V - 3.6V).
  • Speed: 133MHz max.*
  • Temperature: Industrial Range -40°C to +85°C.

Notes: * standard number/value but depends on assembly version.

Scroll Title
anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins

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MIO PinSchematicU7 PinNotes
MIO1SPI-CSCS#-
MIO3SPI-DQ1/M1SO/IO1-
MIO4SPI-DQ2/M2WP#/IO2-
MIO2SPI-DQ3/M3HOLD#/IO3-
MIO5SPI-DQO/M0SI/IO0-
MIO6SPI-SCK/M4SCK-


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Scroll Title
anchorTable_OBP_I2C_EEPROM
titleI2C address for EEPROM

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I2C DeviceI2C AddressDesignatorNotes
2K Serial EEPROMs with EUI-48™

0xA6 (write)
0xA7 (read)
0x53 (7bit)

U24-
512Kb Serial EEPROM0xA0 (write)

0xA1 (read)
0x50 (7bit)

U21-


ADCs

The TE0716 module has 10x 12-Bit Low Power SAR Analog-to-Digital Converter, fully differential input, signed output, with SPI−compatible interface (NCD98011), which are connected to the FPGA PL BANK34.

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Scroll Title
anchorTable_OBP_ADC
titleADC to PL interface PL and pins

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DesignatorSchematicPL PinNotes
U1

S0_CLK          

S0_CSN          

S0_OUT          

J18

J16

K18

3.3V Max Voltage on any pin.
U2

S5_CLK          

S5_CSN          

S5_OUT          

M21

T16

T17

3.3V Max Voltage on any pin.
U3

S1_CLK          

S1_CSN          

S1_OUT          

L18

J21

L19

3.3V Max Voltage on any pin.
U4

S6_CLK          

S6_CSN          

S6_OUT          

J22

K21

J20

3.3V Max Voltage on any pin.
U10

S2_CLK          

S2_CSN          

S2_OUT          

M22 

R21 

R20 

3.3V Max Voltage on any pin.
U11

S7_CLK          

S7_CSN          

S7_OUT          

L22 

M20 

M19 

3.3V Max Voltage on any pin.
U15

S3_CLK          

S3_CSN          

S3_OUT          

J17 

J15 

L17 

3.3V Max Voltage on any pin.
U16

S8_CLK          

S8_CSN          

S8_OUT          

M17 

N18 

N17 

3.3V Max Voltage on any pin.
U17

S4_CLK          

S4_CSN          

S4_OUT          

P17 

L21 

P18 

3.3V Max Voltage on any pin.
U19

S9_CLK          

S9_CSN          

S9_OUT          

K15 

P21 

P20 

3.3V Max Voltage on any pin.


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Scroll Title
anchorTable_OBP_ETH
titleEthernet PHY to Zynq SoC connections

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U8 Pin Signal NameConnected toSignal DescriptionNote

TX_CLK

ETH-TXCK        MIO16

RGMII Transmit Clock

-

TXD[0..3]

ETH-TXD0..3MIO17..20

RGMII Transmit Data

-

TX_CTRL

ETH-TXCTL       MIO21

RGMII Transmit Control

-

RX_CLK

ETH-RXCK        MIO22

RGMII Receive Clock

-

RXD[0..3]

ETH-RXD0..3MIO23..26

RGMII Receive Data

-

RX_CTRL

ETH-RXCTL       MIO27

RGMII Receive Control

-

MDC

ETH-MDCMIO52

Management data clock reference

-

MDIO

ETH-MDIOMIO53

Management data

-

RESETn

PHY-RST         MIO51, U18

Hardware reset. Active low.

Shared with U18 (RESETB) USB

MDIP[0..3] MDIN[0..3]

PHY_MDI0..3_P
PHY_MDI0..3_N		JP1

Media Dependent Interface

-

XTAL_IN

ETH-CLK         U9

Reference Clock Input

see also Clock Sources section

LED[0..1]

PHY_LED0..1FPGA BANK 33

LED output

-


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Scroll Title
anchorTable_OBP_USB
titleUSB PHY to Zynq SoC connections

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U18 Pin Signal NameConnected toSignal DescriptionNote

CLKOUT

OTG-CLK         MIO36ULPI Output Clock-

DATA[0..3]

OTG-DATA0..3MIO32..35

ULPI bi-directional data bus

-

DATA[4]

OTG-DATA4       MIO28ULPI bi-directional data bus -

DATA[5..7]

OTG-DATA5..7MIO37..39ULPI bi-directional data bus -

DIR

OTG-DIR         MIO29

Controls the direction of the data bus

-

STP

OTG-STP         MIO30

terminates transfers PHY input

-

NXT

OTG-NXT         MIO31

control data flow into and out of the PHY

-

RESETB

PHY-RST MIO51, U8reset and suspend the PHY. Active low.Shared with U8 (RESETn) Ethernet

DP

USB_OTG_D_PJP2-64

D+ pin of the USB cable

3.3V Voltage level

DM

USB_OTG_D_N     JP2-65

D- pin of the USB cable

3.3V Voltage level

ID

USB_OTG_ID      JP2-66ID pin of the USB cable3.3V Voltage level

CPEN

USB_VBUS_EN     JP2-67

Controls the external VBUS power switch

3.3V Voltage level

VBUS

USB_VBUS        JP2-68

For RVBUS connection

Max. voltage: 5.5V

REFCLK

OTG-RCLK        U14 

ULPI clock input

see also Clock Sources section


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Scroll Title
anchorTable_OBP_FTDI
titleUSB FTDI to Zynq SoC connections

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U39 Pin Signal NameConnected toSignal DescriptionNote
DPD_JTAG_PJ13-2USB Data Signal Plus3.3V Voltage level
DMD_JTAG_NJ13-3USB Data Signal Minus3.3V Voltage level
ADBUS0TCKJP2-8,
TCK_0 (FPGA PL BANK 0)		Clock Signal Output3.3V Voltage level.
MPSSE Mode
ADBUS1TDIJP2-11,
TDI_0 (FPGA PL BANK 0)		Serial Data Output3.3V Voltage level.
MPSSE Mode
ADBUS2TDOJP2-10,
TDO_0 (FPGA PL BANK 0)		Serial Data Input3.3V Voltage level.
MPSSE Mode
ADBUS3TMSJP2-7,
TMS_0 (FPGA PL BANK 0)		Output Signal Select3.3V Voltage level.
MPSSE Mode
BDBUS0UART_TX_OBU36-5Asynchronous serial TXDU36-3 Bus Switch pin connects later this signal to UART_RX_ZYNQ when UART_OB_DISABLE is low or floating.
BDBUS1UART_RX_OBU36-6Asynchronous serial RXDU36-2 Bus Switch pin connects later this signal to UART_TX_ZYNQ when UART_OB_DISABLE is low or floating.
OSCIOSCI
Oscillator input-
EECS, EECLK, EEDATAEECS, EECLK, EEDATAU40-1..3EEPROM interface-
-UART_OB_DISABLEJP1-11Enable signal of the FTDI-PS_UART Bus Switch U36.Active Low!.


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Power supply with minimum current capability of 3.0 A (TBD*) for system startup is recommended.

* TBD - To Be Determined

Power Consumption

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titlePower Consumption

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Power Input PinTypical Current
+5.0VTBD*
+5.0V_VAAless than 250mA (TBD*)


* TBD - To Be Determined

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Scroll Title
anchorFigure_PWR_PD
titlePower Distribution


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Power-On Sequence

The TE0716 has only one common "PGOOD" signal (from U37, U43, U45 and U46), and there is no Enable for the board. You could control the startup of the board IC, by controlling the +5.0V and the +5.0V_VAA input signals only.

Scroll Title
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titlePower Sequency


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Voltage Monitor Circuit

The TE0716 has also a Voltage Monitor IC. It keeps nRST signal low if the FPGA core voltage (+1.0V) drops under 0.84V or the 3.3V power supply drops to 2.94V or less.

Power Good signal is unique and comes from the power supplies IC U37, U43, U45 and U46, as you can see in the previous section "Power-On Sequence", and also could make nRST to remain low until PGOOD is high.

See also "Reset process." section in "Configuration Signals" for additional information.

Scroll Title
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titleVoltage Monitor Circuit


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titlePower Sequency
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Voltage Monitor Circuit

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titleVoltage Monitor Circuit
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Power Rails

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titleModule power rails.

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Power Rail Name

B2B Connector

JP1 Pin

B2B Connector

JP2 Pin

DirectionNotes
+5.0V1, 23, 351, 23, 35InputMain Supply voltage from the carrier board
+5.0V_VAA43, 44-InputAnalog Supply voltage from the carrier board
+3.3V (VREF_JTAG)-5OutputJTAG reference voltage.


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Page properties
hiddentrue
idComments
  • This section is optional and only for modules.

  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    PD:6 x 6 SoM LSHM B2B ConnectorsPD:
    6 x 6 SoM LSHM B2B Connectors

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Scroll Title
anchorTable_TS_AMR
titlePS absolute Absolute maximum ratings

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SymbolsDescriptionMinMaxUnitReference
+5.0VMain Supply voltage from the carrier board-0.36.0VNCV6357 Datasheet
NCV6323 Datasheet
NCP160 Datasheet
+5.0V_VAAAnalog Supply voltage from the carrier board-0.36.0VNCP160 Datasheet
MIO 500I/O input voltage for MIO bank 500-0.43.85VXilinx DS187 Datasheet
MIO 501I/O input voltage for MIO bank 501-0.42.35VXilinx DS187 Datasheet
PL HRI/O input voltage for HR banks-0.43.85VXilinx DS187 Datasheet
ADCx_P/NI/O input voltage for ADCs analog inputs-0.33.63VNCD98011 Datasheet


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Scroll Title
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titleRecommended operating conditions.

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ParameterMinMaxUnitsReference Document
+5.0V Main Supply input voltage
from the carrier board		4.05.5V

7WB3125 Datasheet

NCV6357 Datasheet

NCV6323 Datasheet

NCP160 Datasheet

+5.0V_VAA Analog Supply input voltage
from the carrier board		3.755.5VNCP160 Datasheet
I/O input voltage for MIO bank 500-0.23.x5VXilinx DS187 Datasheet
I/O input voltage for MIO bank 501-0.22.x0VXilinx DS187 Datasheet
I/O input voltage for HR banks-0.23.x5VXilinx DS187 Datasheet
I/O input voltage for ADCs analog inputs-0.23.x4VNCD98011 Datasheet


Physical Dimensions

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Page properties
hiddentrue
idComments

Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706TE0716

    DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706TE0716


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titleTrenz Electronic Shop Overview

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Trenz shop TEXXXX TE0716 overview page
English pageGerman page


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titleBoard hardware revision number.


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Document Change History

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titleDocument change history.

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DateRevisionContributorDescription

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change list

  • Correction power rail

2020-10-30v.85Guillermo Herrera
  • initial release

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