Page History

...

We need Hard Debug. I mark MII pins from the RMII to MII wrapper for debugging. In Vivado analyzer I see MAC addresses in the MII RX Data bus, hence the packets do get into FPGA and do get converter converted from RMII to MII also. So where is the problem?

More reading, this time Ethernet Lite user guide. If packets are on MII bus, and if they are at all valid (even if FCS is missing etc) then at least some bytes should be visible in the RX ping-pong buffers, right?

...

Lets take out network cable, and reset this bit, now it stays 0. Cable back, reading again. And again the buffer valid bit goes 1.

So why id did LwIP never see any incoming packets?

...

So why did take so long to make it work? Maybe because I was looking at existing reference designs for too long. Digilent Nexys4 has RMII PHY but I was not able to find any reference designs at Digilent website. Then as second option there is Artix based board from Avnet with RMII PHY, but it has only been launched and the support materials are not yet online. I found also one Lattice XO2 based board that has RMII PHY and promises "source code" but in the install archive are only JEDEC files. So all my search for any FPGA example code for RMII PYH's ended up in void.

The Block Diagram of the System is bit more complicated as it should be: the CLKOUT block is small IP Core that sends a global clock to IO buffer with no phase delay using DDR I/O FlipFlop. This clock has exactly same phase as the TXD outputs to PHY. This output was only used for measurements, it is not wired to the PHY ref clock at all.

Clocking is also too complicated, during debugging I derived the PHY clock from System Clock, and System Clock from MGT Clock. Of course there was no need for this...