Page History

Custom_table_size_100

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Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"

Template Change history:

Version	Changes	Author
4.2	Changes Xilinx to AMD	ED
4.1	Minor changes Notes Tables	ED
4.0	Rework for smaller TRM which can be generated faster Reduce Signal Interfaces Pin Reduce On Board Periphery Reduce Power Move Configuration Signals from Overview to own section	JH
3.12	Version History changed from list to table all changed title-alignment for tables from left to center	ma
3.11	update "Recommended Operating Conditions" section
3.1	New general notes for temperature range to "Recommended Operating Conditions"
3.02	add again fix table of content with workaround to use it for pdf and wiki Export Link for key features examples Notes for different Types (with and without Main FPGA) Export Link for Signals, Interfaces and Pins examples Notes for different Types (Modul, Modul Hybrid, Evalboard, Carrier)
3.01	remove fix table of content and page layout ( split page layout make trouble with pdf export) changed and add note to signal and interfaces, to on board periphery section ...(not finished)
3.00	→ separation of Carrier/Module and evaluation kit TRM
2.15	add excerpt macro to key features
2.14	add fix table of content add table size as macro

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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title-alignment	center
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables

Scroll Title

anchor	Table_tablename
title-alignment	center
title	Text

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Example	Comment
1	2

The anchors of the Scroll Title should be named consistent across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchor from external : <page url>#<pagename without space characters>-<anchorname>

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-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Scroll Ignore
Download PDF version of this document.

Overview

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

The Trenz Electronic TEB2000 carrier board provides functionality for development, evaluation and testing purposes of Trenz 4 x 5 cm SoMs (System on Module).

The carrier board is equipped with a broad range of various components and connectors for different configuration setups and needs. On-module functional components and multipurpose I/Os of the SoM's PL and PS logic are connected via board-to-board connectors to the carrier board components and connectors for easy user access.

See page "4 x 5 SoM Carriers" for more information about the SoM's supported by the TE0703 TEB2000 Carrier Board.

Refer to http://trenz.org/teb2000-info (Links is correct, url should be redirect to Resources Page, but is not) for the latest online version of this manual and other available documentation.

Key Features

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

→ See examples for different types <Series Name> TRM Template section examplesexamples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures

Excerpt

On Board:
- System Controller (SC) (LCMXO2-1200HC-4TG144I¹⁾)
- Mini USB for JTAG and UART connection (FTDI FT2232H), compatible with AMD and other vendor development tools
- Mini USB second UART connection (FTDI FT230XQ)
- SDIO port expander
- 4 x User LEDs
  - D1 and , D2 are connected to the SC, their function depends on the firmwareSC (firmware-dependent functionality)
  - D3, D4 connected to SC and D3 and D4 are connected to the SC and the 4 x 5 SoM and can be directly controlled by it
- 2 x User push button
  - Connected to the SC , the fuction is firmware depend(firmware-dependent functionality)
  - Currently used for Hard- and Soft-Reset
- 4 User DIP switches
  - Enable/disable update of the SC
  - MIO0 (readable accessible signal by SC and SoM)
  - 2 "mode" bits
Interface:
- Trenz 4 x 5 SoM socket
  - 3 x Samtec LSHM series high-speed connectors
- Micro SD card connector
- 2 x VG96 backplane connectors assembly option (mounting holes and solder pads)
- Mini or Normal USB for SoM USB-OTG connection ¹⁾
- RJ45 GbE connector
Power:
- Overvoltage-, undervoltage- and reversed- supply-voltage-protection
- Barrel jack (2.1 mm) for 5V power supply input
Dimension:
- 100 mm x 64.5 mm
Notes

¹⁾Depends on assembly variant

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram

Note

All created DrawIOs should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD

Scroll Title

anchor	Figure_OV_BD
title-alignment	center
title	TExxxx TEB2000 block diagram

Scroll Ignore

draw.io Diagram

top

border	true

diagramName	TEB2000_OV_BD
simpleViewer	false
width
links	auto
tbstyle	hidden
diagramDisplayName
lbox	true
diagramWidth	630
revision	1113

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Main Components

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Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

System Controller (SC) CPLD, U5
USB-to-JTAG/UART-FTDI, U4, U12
UART LEVEL Shifter, U8
SDIO Port Expander, U2
I²C Repeater, U7
Power Input Protection, U11
DCDC, U3
USB Power Supply Switch, U1
Reset / Push button, S1, S6 NEU
4x Dip Switches, S2
ULED1 D1 (red), D2 (green)
FLED1 con to SC PL9A, D3 (red), D4 (green)
Ethernet jack, J14
Samtec Razor Beam™ LSHM-150/130 B2B connector, JB1, JB2, JB3
Footprint for VG96 Connector / VG96 Connector, J1 and J2
+5V power jack, J13
microSD Card Socket, J3
Bank IO Voltages jumper, J5, J8, J9, J10
Mini USB Type B jack, J4 (FT2232H), J21 (FT230XQ)
USB Host Connector, either a USB A jack, J6 or a Micro USB, J12

Note
For more information regarding how to add board photos, Please refer to "Diagram Drawing Guidline" .

Scroll Title

anchor	Figure_OV_MC
title-alignment	center
title	TExxxx main components

Scroll Ignore

draw.io Diagram

border

true

diagramName

TEB2000-01_Figure_OV_MC

simpleViewer

false

width

links

auto

tbstyle

top

lbox

true

diagramWidth

641

revision

2

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

U1, USB Power Supply Switch
U2, SDIO Port Expander
U3, DCDC
U4, U12, USB-to-JTAG/UART-FTDI
U5, System Controller (SC) CPLD
U7, I²C Repeater
U8, UART LEVEL Shifter
U11, Power Input Protection

S1, Push button Reset
S2, 4x Dip Switches
S6, Push button Soft Reset

J1, J2, Footprint for VG96 Connector / VG96 Connector
J3, Socket microSD Card
J4, Mini USB Type B jack (FT2232H)
J5, J8, J9, J10, Jumper Bank IO Voltages
J6, or J12, USB Host Connector, either a USB A jack or a Micro USB
J13, +5V power jack
J14, Ethernet jack
J21, Mini USB Type B jack (FT230XQ)

Dx, U-LED red and green (D1, D2), F-LED red and green (D3, D4)

Initial Delivery State

Note
For more information regarding how to add board photos, Please refer to "Diagram Drawing Guidline" .

Scroll Title

anchor	Figure_OV_MC
title-alignment	center
title	TEB2000 main components

Scroll Ignore

draw.io Diagram

border	true

diagramName	TEB2000-01_Figure_OV_MC
simpleViewer	false
width
links	auto
tbstyle	hidden
diagramDisplayName
lbox	true
diagramWidth	641
revision	4

Scroll Only
Image Added

System Controller (SC), U5
USB-to-JTAG/UART-FTDI, U4
USB-to-UART-FTDI, U12
UART Level Shifter, U8
SDIO Port Expander, U2
I²C Repeater, U7
Power Input Protection, U11
DCDC, U3
USB Power Supply Switch, U1
Reset / Push button, S1, S6
4x Dip Switch, S2
LED D1 (red), D2 (green)
LED D3 (red), D4 (green)
Ethernet Jack, J14
Samtec Razor Beam™ LSHM-150/130 B2B connector, JB1, JB2, JB3
Assembly option for VG96 Connector, J1, J2
Power Jack, J13
microSD Card Socket, J3
Bank IO Voltages jumper, J5, J8, J9, J10
Mini USB Type B Jack, J4 (FT2232H), J21 (FT230XQ)
USB Host Connector, J6 (USB A) or J12 (Micro USB)

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

Scroll Title

anchor	Table_OV_IDS
title-alignment	center
title	Initial delivery state of programmable devices on the module

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes
EEPROM	Preprogrammed with Microchip programmer license	Do not overwrite!
System Controller	Preprogrammed with Firmware	Visit TEB2000 Firmware for further information.

Signals, Interfaces and Pins

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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Note

For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note
Table with all connectors and Designator List of different interfaces per connector IO CNT (for FPGA IOs where functionality can be changed by customer)

Connectors

Scroll Title

anchor	Table_OVSIP_IDSC
title-alignment	center
title	Initial delivery state of programmable devices on the module	Board Connectors

scroll-scroll-tablelayout

widths

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Storage device name

Content

Notes

EEPROM

Preprogrammed with AMD programmer license

Do not overwrite!

System Controller CPLD

Preprogrammed
with SC CPLD Firmware

The Firmware sources are available for modification to your needs.
Visit TE0703 Firmware for further information.

The carrier is shipped in the following configuration:

VCCIO -A/B/C/D voltage selection jumpers are all set to 1.8 V.

SD IO Voltage jumper J11 is set to 1.8 V.

VBat jumper J7 is set to gnd.

Switch S1 configured as reset button in CPLD.

The Base Board is shipped with two VG96 backplane connectors, which are not soldered.

S2 DIP switches are configured as follows:
SwitchPositionSignal nameDescriptionS2-1OFFCM1

PGOOD signal active state set to high.

S2-2ONCM0

FPGA access to SoM.

See TE0703 Firmware section "JTAG" for access options.

S2-3

ONJTAGENS2-4ONMIO0Boot source set to SD Card.
See TE0703 Firmware section "Boot Mode" for access options.

Signals, Interfaces and Pins

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For subsection examples see: <Series Name> TRM Template section examples

Note
Table with all connectors and Designator List of different interfaces per connector IO CNT (for FPGA IOs where functionality can be changed by customer)

Connectors

Scroll Title

anchor	Table_SIP_C
title-alignment	center
title	Board Connectors

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orientation	portrait
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Connector TypeDesignator
ConnectionEndpointInterfaceIO CNTNotesVG96J1JB1IO

48 SE / 24 DIFF

To SoM via JB13x 2.54 mm Pin HeaderJ7JB1Battery Voltage1To SoM via JB1.
1.2 to 1.5 VoltRJ-45 Ethernet
J14JB1Ethernet8Gbit capable, Phy MDI to SoM, LEDs to SC
VG96J2JB2IO48 SE / 24 DIFFTo SoM via JB2VG96J2JB2IO18 SE / 9 DIFFTo SoM via JB2VG96J1JB3IO36 SE / 18 DIFFTo SoM via JB3Micro USB
Type A/B
or
USB Type AExclusive J6 or J12JB3USB 2.0 OTG3To SoM, Data ± and ID. Only on USB jack possibleVG96J2SCIO18To SC X0 unto X17B2BJB2SCJTAG4To SCB2BJB2SCReset, RESIN1To SCMini USB Type BJ4SCUSB 2.02To Carrier FTDIMini USB Type BJ21SCUSB 2.02To Carrier FTDIB2BJB1SCUART2UART to SoM for application
B2BJB1SCUART2UART to SoM for HSS/System Boot
microSD Card socketJ3SC or SoMSD6VG96J1SoM and SCI²C2To SoM via JB1and SC

Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delete the Test Point section.

Example:

Test PointSignalNotes¹⁾TP1PWR_PL_OK

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Connector Type	Designator	Interface	IO CNT
VG96	J1	JB1 - IO	48 SE / 24 DIFF
VG96	J1	JB3 - IO	36 SE / 18 DIFF
VG96	J1	B2B/SC - I²C	2
Micro USB Type A/B ¹⁾	J12	JB3 - USB 2.0 OTG	2
RJ-45 Ethernet	J14	B2B - ETH	8
RJ-45 Ethernet	J14	SC - ETH LED	4
VG96	J2	JB2 - IO	65 SE / 32 DIFF
VG96	J2	SC - IO	16
Mini USB Type B	J21	SC - USB 2.0	2
microSD Card socket	J3	SDIO	SDIO ²⁾
Mini USB Type B	J4	FTDI - USB 2.0	2
USB Type A ¹⁾	J6	JB3 - USB 2.0 OTG	2
B2B	JB1	J1 - IO	48 SE / 24 DIFF
B2B	JB1	2 x UART or 4 x IO	4
B2B	JB1	I2C or 2 x IO	2
B2B	JB1	SC - IO	2
B2B	JB1	SDIO	SDIO ²⁾ or 6 x IO
B2B	JB1	ETH - MDI	ETH
B2B	JB2	J2 - IO	65 SE / 32 DIFF
B2B	JB2	SC - JTAG	4
B2B	JB2	SC - Reset	1
B2B	JB2	2 x LED or 2 x IO	2
B2B	JB3	J1 - IO	36 SE / 18 DIFF
B2B	JB3	USB	USB

¹⁾ Depending on the variant only one of the USB connectors is assembled.
²⁾ Depending on firmware microSD Card socket is connected to SC or SoM. Refer to TEB2000 CPLD Firmware for further information.

Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delete the Test Point section.

Example:

Test Point	Signal	Notes¹⁾
TP1	PWR_PL_OK

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Scroll Title

anchor	Table_SIP_TPs
title-alignment	center
title	Test Points Information

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Test Point	Signal	Notes
TP1	5VIN
TP2	5VIN
TP3	VIN
TP4	VIN
TP5	3.3V
TP6	3.3V
TP7	VCCIOA
TP8	VCCIOA
TP9	VCCIOB
TP10	VCCIOB
TP11	VCCIOC
TP12	VCCIOC
TP13	VCCIOD
TP14	VCCIOD
TP15	M1.8VOUT
TP16	M1.8VOUT
TP17	M3.3VOUT
TP18	M3.3VOUT
TP19	UART_VBUS
TP20	UART_VBUS
TP21	VCCJTAG
TP22	VCCJTAG
TP23	3.3V_SD
TP24	3.3V_SD
TP25	USB-VBUS_R
TP26	USB-VBUS_R
TP27	ETH-VCC
TP28	ETH-VCC
TP29	Vbus
TP30	Vbus
TP31	CM1
TP32	CM0
TP33	MIO0
TP34	JTAGEN

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

Chip/Interface	Designator	Connected To	Notes
ETH PHY	U10	B2B connector J1 SoC MIO	Gigabit ETH PHY

Scroll Title

anchor	Table_OBP
title-alignment	center
title	On board peripherals

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Chip/Interface	Designator	Connected To	Notes
System Controller	U5	B2B Connector FTDI (FT2232H) U4 FTDI (FT230XQ) U12 SD Port Expander U2 Push button S1 DIP Switch S2 All LEDs	Visit TEB2000 CPLD Firmware for further information.
FTDI FT2232H	U4	SC J4	JTAG/UART for Application
FTDI FT230XQ	U12	SC J21	UART for HSS/System Boot
EEPROM	U10	FTDI	Preprogrammed with Microchip programmer license. Do not overwrite!
SD IO Port Expander	U2	SC B2B Connector JB1 microSD Card J3
I2C Repeater	U7	VG96 J1 B2B JB1 SC U5
Oscillator	U6	FTDI U4	12 MHz

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id	Comments

For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

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id	Comments

Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)

Scroll Title

anchor	Table_OV_CNTRL
title-alignment	center
title	Controller signal.

Scroll Table Layout

orientation	portrait
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repeatTableHeaders	default
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sortEnabled	false
cellHighlighting	true

Signal Name	Connector.Pin	Direction¹⁾	Description
S1	S1.2 / S1.4	IN	Push button ²⁾
SRST	S6.2 / S6.4	IN	Push button
SRST	JB2.56	OUT	Push button
CM1	S2.8	IN	DIP Switch ²⁾
CM0	S2.7	IN	DIP Switch ²⁾
JTAGEN	S2.6	IN	DIP Switch ²⁾
MIO0	S2.5	IN	DIP Switch ²⁾
VCCIOA	J5.2	IN	SoM IO Bank supply ³⁾
VCCIOB	J8.2	IN	SoM IO Bank supply ³⁾
VCCIOC	J9.2	IN	SoM IO Bank supply ³⁾
VCCIOD	J10.2	IN	SoM IO Bank supply ³⁾
SD_CD	J3.9	IN	SD Card socket Detect Signal
VBUS_V_EN	JB3.54	IN	Enables USB Host Bus Voltage
USB-VBUS	JB3.56	OUT	Signal to SoM
RESIN	JB2.17	OUT	Reset signal ²⁾
EN1	JB1.27	OUT	Power enable signal ²⁾
PGOOD	JB1.29	INOUT	Power good and/or Boot mode select signal ²⁾
MODE	JB1.31	INOUT	Boot mode select signal ²⁾
NOSEQ	JB1.8	INOUT	Power Management and/or Select JTAG target on the SoM ²⁾
PROGMODE	JB1.90	INOUT	Select JTAG target on the SoM ²⁾
MIO14 / MIO15	JB1.91 / JB1.86	INOUT	UART to SoM (FT2230H) ²⁾
MIO12 / MIO13	JB1.100 / JB1.98	INOUT	UART to SoM (FT230XQ) ²⁾
MIO10-SCL / MIO10 MIO10-SDA / MIO11	J1A.A1 / JB1.96 J1A.A2 / JB1.94	INOUT	I2C bus ²⁾
TMS_B / TDI_B / TDO_B / TCK_B	JB2.94 / JB2.96 / JB2.98 / JB2.100	Signal-dependent	JTAG configuration and debugging interface. JTAG reference voltage: VCCJTAG

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

²⁾ Firmware dependent. Refer to TEB2000 CPLD Firmware for further information.
³⁾ Select 1.8V or 3.3V via jumper. Refer to 4 x 5 Module Integration Guide for further information.

Power and Power-On Sequence

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Enter the default value for power supply and startup of the module here.

Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

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List of all power rails which are accessible by the customer

Main Power Rails and Variable Bank Power

Scroll Title

anchor	Table_PWR_PR
title-alignment	center
title	Module power rails.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
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sortEnabled	false
cellHighlighting	true

Power Rail Name/ Schematic Name	Connector.Pin	Direction¹⁾	Notes
5VIN	J13.1	IN
5VIN	J2A.A1 / J2A.A2	OUT
3.3V	J1C.C31 / J2C.C31 / JB1.2 / JB1.4/ JB1.6/ JB1.14/ JB1.16 / JB2.1 / JB2.3 / JB2.5 / JB2.7	OUT
USB-VBUS_R	J6.1 / J12.1	OUT
USB-VBUS	JB3.56	OUT
M1.8VOUT	JB1.40	IN
M1.8VOUT	J5.3 / J8.3 / J9.3 / J10.3	OUT
M3.3VOUT	JB2.9 / JB2.11	IN
M3.3VOUT	J5.1 / J8.1 / J9.1 / J10.1 / J1C.C32 / J2C.C32	OUT
VCCJTAG	JB2.92	IN
ETH-VCC	JB1.13	IN
ETH-VCC	J14A.1	OUT
VCCIOA	JB1.10 / JB1.12 / J1B.B1	OUT	Selection via J5 ²⁾
VCCIOB	JB2.2 / JB2.4 / J1B.B32	OUT	Selection via J8 ²⁾
VCCIOC	JB2.6 / J2B.B32	OUT	Selection via J9 ²⁾
VCCIOD	JB2.8 / JB2.10 / J2B.B1	OUT	Selection via J10 ²⁾

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

²⁾ Select 1.8V or 3.3V via jumper. Refer to 4 x 5 Module Integration Guide for further information.

Recommended Power up Sequencing

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List baseboard design hints for final baseboard development.

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title	Baseboard Design Hints

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Sequence	Net name	Recommended Voltage Range	Pull-up/down	Description	Notes
0	-	-	-	Configuration signal setup.	See Configuration and System Control Signals.
1	5VIN	5 V (± 5 %)	-	Main Power supply.	Carrier and SoM power supply. Minimal 1 A, maximal 4A. Power consumption depends mainly on design and cooling solution.
2	M3.3VOUT / M1.8VOUT	3.3 V (± 3 %) / 1.8 V (± 3 %)	-	SoM generated output voltages.	These voltages can be used to supply bank voltages, to supply periphery and/or as power good signal to enable external power regulators. Important: Consider maximum power consumption.
3	-	-	-	Apply voltages to Carrier powered external IO when voltages under point 2 are present.

Board to Board Connectors

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This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors
Include Page
6 x 6 SoM LSHM B2B Connectors
6 x 6 SoM LSHM B2B Connectors

Include Page

	4 x 5 SoM LSHM B2B Connectors
	4 x 5 SoM LSHM B2B Connectors

Technical Specifications

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List of all power rails which are accessible by the customer

Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

This Table shows the real values and reasons for the limits, so that they do not get lost.

Power Rail / Schematic Name	Description	Min	Max	Unit	Notes	Reason for the limit
SD Card Limits	Limits for 3.3 V and 1.8 V SD Card supply. Only Recommanded values are given.	Rec: 2.7 1.7	Rec: 3.6 1.95	V	Supplied by M3.3VOUT and optional by M1.8VOUT, when SD IO Jumper is to 1.8 V.

5VIN	Carrier supply voltage rail before the input protection.	Abs: -40 Rec: 4.75	Abs: 60 Rec: 5.5	V	Voltages outside of the range 4.06 to 5.58 V will trigger the input protection. Rec.= USB Bus Voltage
VCCIOA	SoM IO Bank Voltage.	-	-	V	Voltage can be supplied by M1.8VOUT, M3.3VOUT or externally by VG96 IO.
VCCIOB	SoM IO Bank Voltage.	-	-	V	Voltage can be supplied by M1.8VOUT, M3.3VOUT or externally by VG96 IO.
VCCIOC	SoM and Carrier Sc IO Bank 2 voltage.	Abs: -0.5 Rec: 1.14	Abs: 3.75 Rec: 3.6	V	Voltage can be supplied by M1.8VOUT, M3.3VOUT or externally by VG96 IO. System Controller Limits: Abs: -0.5 to 3.75 Rec VCC: 2.375 to 3.6 Rec IO: 1.14 to 3.6	Limited by Absolute Maximum Values of the Sc.
VCCIOD	SoM IO Bank Supply Voltage.	-	-	V	Voltage can be supplied by M1.8VOUT, M3.3VOUT or externally by VG96 IO.
M1.8VOUT	SoM supplied voltage. Range based on Carrier (± 3 %). Consult SoM requirements.	Abs: -0.3	Abs: 4.9	V	When suppling SC IO Bank 2 via VCCIOC, the limit ist -0.5 to 3.75 V.
M3.3VOUT	SoM supplied voltage.	Abs: -0.5	Abs: 4.6	V	When suppling SC IO Bank 2 via VCCIOC, the limit ist -0.5 to 3.75 V. When suppling a SD Card, SD Card limits are 2.7 to 3.6 V.	M3.3VOUT is limited by U2 in the range -0.5 to 4.6 V.
VBAT	Dependent on SoM requirements.	-	-	V
VCCJTAG	SoM supplied JTAG Reference Voltage for Carrier SC IO Bank 3.	Abs: -0.5	Abs: 3.75	V	System Controller Limits: Abs: -0.5 to 3.75 Rec VCC: 2.375 to 3.6 Rec IO: 1.14 to 3.6	Limited by Absolute Maximum Values of the Sc.
ETH-VCC	ETH Bias Voltage from SoM.	-	-	V

Absolute Maximum Ratings ^*)

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Power Rail / Schematic Name	Description	Min	Max	Unit
5VIN	Main input power supply	-0.3	60	V
VCCIOA ^{1) 2)}	Module power supply.	-	-	V
VCCIOB ^{1) 2)}	Module power supply.	-	-	V
VCCIOC ^{1) 2)}	Module and Carrier power supply.	-0.5	3.75	V
VCCIOD ^{1) 2)}	Module power supply.	-	-	V
M1.8VOUT	Module and carrier power supply.	-0.3	1.95	V
M3.3VOUT	Module and carrier power supply.	-0.3	3.6	V
VCCJTAG	JTAG Reference Voltage

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Test PointSignalDirection ¹⁾NotesTP15VININCarrier supply voltageTP25VININCarrier supply voltageTP3VININCarrier supply voltage after protection circuitTP4VININCarrier supply voltage after protection circuitTP53.3VOUTCarrier generatedTP63.3VOUTCarrier generatedTP7VCCIOAINIO Voltage, generted by SoMTP8VCCIOAINIO Voltage, generted by SoMTP9VCCIOBINIO Voltage, generted by SoMTP10VCCIOBINIO Voltage, generted by SoMTP11VCCIOCINIO Voltage, generted by SoMTP12VCCIOCINIO Voltage, generted by SoMTP13VCCIODINIO Voltage, generted by SoMTP14VCCIODINIO Voltage, generted by SoMTP15M1.8VOUTINIO Voltage, generted by SoMTP16M1.8VOUTINIO Voltage, generted by SoMTP17M3.3VOUTINIO Voltage, generted by SoMTP18M3.3VOUTINIO Voltage, generted by SoMTP19UART_VBUSINCarrier USB Bus VoltageTP20UART_VBUSINCarrier USB Bus VoltageTP21VCCJTAGINJTAG Reference Voltage generated, by the SoMTP22VCCJTAGINJTAG Reference Voltage generated, by the SoMTP233.3V_SDOUTCarrier microSD card VoltageTP243.3V_SDOUTCarrier microSD card VoltageTP25USB-VBUS_ROUTCarrier USB Bus VoltageTP26USB-VBUS_ROUTCarrier USB Bus VoltageTP27ETH-VCCINTP28ETH-VCCINTP29VbusINExternal/FTDI USB Bus VoltageTP30VbusINExternal/FTDI USB Bus VoltageTP31CM1IN

DIP Switches

TP32CM0INTP33MIO0INTP34JTAGENIN

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

Chip/InterfaceDesignatorConnected ToNotesETH PHYU10

B2B connector J1
SoC MIO

Gigabit ETH PHY Scroll Title

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Chip/InterfaceDesignatorConnected ToNotes

System Controller

U5

SoM
FTDI
JB1 B2B connector
UART, 6x MIO, 5x Config signals
JB2 B2B connector
JTAG, RESIN and 18 IOs
SD Port Expander
Channel B1, Channel Select, SD Interrupt
Push button S1
DIP Switch S2
All LEDs

The Firmware sources are available for modification to your needs.
Visit TEB2000 CPLD Firmware for further information.

FTDI FT2232H

U4

SC
J4

UART for Application

EEPROM

U10

FTDI

Preprogrammed with AMD programmer license.

Do not overwrite!

FTDI FT230XQ

U12

SC
J21

UART for HSS/System Boot

Oscillator

U6

U4 FTDI

12 MHz

SD IO Port Expander

U2

SC
Via JB1 B2B connector to SoM
microSD Card J3

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For example subsections see: <Series Name> TRM Template section examples

Configuration and System Control Signals

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Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)

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Physical defined Signals

Connector.Pin

Signal Name

Endpoint

Direction¹⁾DescriptionS1.2 / S1.4S1SC.BANK-0.114IN

Reset push button.

Functions are firmware dependant.
Visit TE0703 CPLD - CC703S for further information.

S6.2 / S2.4SRSTJB3.56OUT

Soft reset push button for SoM.

S2.1CM1SC.BANK-1.75INS2.2CM0SC.BANK-1.76INS2.3JTAGENSC.BANK-0.120INS2.4MIO0JB1.88INJ5.2VCCIOAJB1.10 / JB1.12 / J1B.VCCIOAINOUTJ8.2VCCIOBJB2.2 / JB2.4 / J1B.VCCIOBINOUTJ9.2VCCIOCJB2.6 / J2B.VCCIOCINOUTJ10.2VCCIODJB2.8 / JB2.10 / J2B.VCCIODINOUT

J3.9

SD_CDSC.Bank-1.93INSD Card socket Interrupt SignalSoftware defined Signals

Connector.Pin

Signal Name

Endpoint

Direction¹⁾DescriptionJB3.54VBUS_V_ENU1.4INEnable from SoMJB3.56USB-VBUSU1.8 → R5 (12K) → JB3.56OUTSignal to SoMU1.5USB_OCSC.BANK-1.73INSignal to SCJB2.17RESINSC.BANK-0.119INOUTBetween SoM and SCJB1.27EN1SC.BANK-1.81INOUTBetween SoM and SCJB1.29PGOODSC.BANK-1.82INOUTBetween SoM and SCJB1.31MODESC.BANK-1.83INOUTBetween SoM and SCJB1.8NOSEQSC.BANK-1.78INOUTBetween SoM and SCJB1.90PROGMODESC.BANK-1.104INOUTBetween SoM and SCJB1.91 / JB1.86MIO14 / MIO15To SC.Bank-1.105 / SC.Bank-1.95INOUTUART to SoM JB1.100 / 98MIO12 / MIO13To SC.Bank-1.100 / SC.Bank-1.99INOUTSecond UART to SoM J1A.MIO10-SCL / J1A.MIO11-SDAMIO10-SCL / MIO10
MIO10-SDA / MIO11

JB1.96 / SC.Bank-1.MIO10
JB1.94 / SC.Bank-1.MIO11

INOUTI2C with 5.1 kOhm pull-up resistors.
To SoM and SC

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Power and Power-On Sequence

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Enter the default value for power supply and startup of the module here.

Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

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List of all power rails which are accessible by the customer

Main Power Rails and Variable Bank Power

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Power Rail Name/ Schematic NameConnector + PinDirection¹⁾Notes5VIN J13.1IN5VIN J2A.5VIN OUT3.3VJ1C.3.3V / J2C.3.3V /
JB1.2 / JB1.4/ JB1.6/ JB1.14/ JB1.16 /
JB2.1 / JB2.3 / JB2.5 / JB2.7OUTUSB-VBUSJ6.1 / J12.1 / JB3.56OUT

M1.8VOUT

JB1.40 / J11.1INFrom SoM

M1.8VOUT

J5.3 / J8.3 / J9.3 / J10.3 /
J11.1OUT

M3.3VOUT

JB2.9 / JB2.11INFrom SoM

M3.3VOUT

J5.1 / J8.1 / J9.1 / J10.1 /
J1C.M3.3VOUT / J2C.M3.3VOUT;OUT

VCCJTAG

JB2.92INFrom SoM

ETH-VCC

JB1.13INFrom SoMVCCIOAJB1.10 / JB1.12INAMD SoM abhängigVCCIOAJ5.2 / J1B.VCCIOAOUTUse jumper J5 to select between M1.8VOUT or M3.3VOUT.VCCIOBJB2.2 / JB2.4INAMD SoM abhängigVCCIOBJ8.2 / J1B.VCCIOBOUTUse jumper J8 to select between M1.8VOUT or M3.3VOUT.VCCIOCJB2.6INAMD SoM abhängigVCCIOCJ9.2 / J2.VCCIOCOUTUse jumper J9 to select between M1.8VOUT or M3.3VOUT.VCCIODJB2.8 / JB2.10INAMD SoM abhängigVCCIODJ10.2 / J2.VCCIODOUTUse jumper J10 to select between M1.8VOUT or M3.3VOUT.

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Recommended Power up Sequencing

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SequenceNet nameRecommended Voltage RangePull-up/down

Description

Notes0---Configuration signal setup.See Configuration and System Control Signals.15VIN5V (± 5 %)-Main Power supply via J13 Barrel Plug 2.1 mm.

Carrier and SoM power supply.
Minimal 1 A, maximal 4A.

Power consumption depends mainly on design and cooling solution.

2M3.3VOUT
(JB2, 9, 11)3.3 V (± 3 %) Schematic-

SoM generated voltage,
which signals operational readyness of the SoM.

3---Apply voltages to Carrier powered external IO
when voltages under point 2 are present.

Board to Board Connectors

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This section is optional and only for modules.

use "include page" macro and link to the general B2B connector page of the module series,

For example: 6 x 6 SoM LSHM B2B Connectors
Include PagePD:6 x 6 SoM LSHM B2B ConnectorsPD:6 x 6 SoM LSHM B2B Connectors Include PagePD:4 x 5 SoM LSHM B2B ConnectorsPD:4 x 5 SoM LSHM B2B Connectors

Technical Specifications

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List of all power rails which are accessible by the customer

Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

Absolute Maximum Ratings ^*)

0
12

SoM supplied voltage.

Range based on Carrier (± 3 %). Consult SoM requirements.

Supplies SC IO Bank 3.

JTAG Reference Voltage from SoM. Consult SoM documentation.

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Power Rail / Schematic Name

Description

Min

Max

Unit

Notes

5VIN

Carrier supply voltage rail before the input voltage protection activates.

V

Voltages in the range 4.06 to 5.58 V will trigger the input protection.

VCCIOA

Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM.

Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96.

-

V

Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT.

VCCIOB

Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM.

Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96.

-

V

Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT.

VCCIOC

Supplies SC IO Bank 2. Connects the external VG96 IO to the SoM and the Carrier SC.

Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96.

-0.5

3.75

V

Limited by Absolute Maximum Values of the Sc.

VCCIOD

Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM.

Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96.

-

V

Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT.

M1.8VOUT

-0.3

M3.3VOUT +0.3 V

V

Voltage limited by Q1/MP5077GG-Z Enabled Pin.

–0.3V to Vcc +0.3 V
(M3.3VOUT-max = 4.6)

Connected SD cards might be destroyed above 1.95 V.

M3.3VOUT

SoM supplied voltage.

Range based on Carrier (± 3 %). Consult SoM requirements.

-0.5

4.6

V

Limited by U2/TXS02612RTWR.

Connected SD cards might be destroyed above 3.6 V.

VCCJTAG

	-0.5	3.75	V
ETH-VCC

ETH Bias Voltage from SoM.
Consult SoM documentation.--V

Power supply for ETH connection.

-

V

¹⁾ Module-dependent.
²⁾ Voltage is intended to be supplied by M1.8VOUT or M3.3VOUT but can also be supplied externally via VG96 connection.

^*) Stresses beyond those listed

under TEB2000 TRM - New Carrier-Board

under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these

or any other conditions beyond those indicated

under TEB2000 TRM - New Carrier-Board

under Recommended Operating Conditions. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can differ depending on assembly variant. The voltage ranges between variants should not be affected (exceptions are possible, depending on custom request)

Temperature Range:

This carrier board is capable to be of being operated at industrial-grade temperatures.

Modules with industrial temperature grade are equipped with components that

, which cover at least the range of -

40°C to 85°C

40 °C to 85 °C.

Please check the operating temperature range of the mounted SoM and peripheral devices, which determines the operating temperature range of the overall system.

The Operating operating temperature range depends also on customer software and hardware design and cooling solution. Please contact us for options.

Voltage Rails:

SoM supplied voltage.
Range based on Carrier (± 3 %). Consult SoM requirements.

Tolerance is ±3 %.
ETH Bias Voltage from SoM.
Consult SoM documentation

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Power Rail / Schematic Name	Description	Min	Max	Unit
5VIN	Main input power supply	4.75	5.25	V
VCCIOA ^{1) 2)}	Module power supply.	-	-	V
VCCIOB ^{1) 2)}	Module power supply.	-	-	V
VCCIOC ^{1) 2)}	Module and Carrier power supply.	1.14	3.6	V
VCCIOD ^{1) 2)}	Module power supply.	-	-	V
M1.8VOUT	Module and carrier power supply.	1.746	1.854	V
M3.3VOUT	Module and carrier power supply.	3.201	3.399	V
VCCJTAG	JTAG Reference Voltage	1.14	3.6	V
ETH-VCC	Power supply for ETH connection

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Power Rail / Schematic Name

Description

Min

Max

Unit

Notes

5VIN

Carrier supply voltage rail before the input voltage protection activates.

4.75

5.25

V

Tolerance is ±5 %.

VCCIOA

Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM.

Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96.

1.75

3.4

V

Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT.

VCCIOB

Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM.

Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96.

1.75

3.4

V

Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT.

VCCIOC

Supplies SC IO Bank 2. Connects the external VG96 IO to the SoM and the Carrier SC.

Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96.

1.2

3.4

V

Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT.

VCCIOD

Intended as Supply Voltage for a SoM IO Bank. Connects the external VG96 IO to the SoM.

Dependent on Carrier and SoM combination, their settings and your external IO devices connected to VG96.

1.75

3.4

V

Voltage intended to be supplied by either M1.8VOUT or M3.3VOUT.

M1.8VOUT

1.75

1.85

V

Tolerance is ±3 %.

M3.3VOUT

SoM supplied voltage.

Range based on Carrier. Consult SoM requirements.

3.2

3.4

V

VCCJTAG

Supplies SC IO Bank 3.

JTAG Reference Voltage from SoM. Consult SoM documentation.

1.2

3.3

V

Values from Schematic.

ETH-VCC

.

-

V

Physical Dimensions

Carrier size: 100 mm x 64.5 mm.
Note that few parts are slightly hanging over the PCB edge. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8 mm.
PCB thickness: 1.64 64 mm ± 10 %.

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guideline" .

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Currently Offered Variants

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Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

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Trenz shop TEXXXX TEB2000 overview page
English page	German page

Revision History

Hardware Revision History

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Set correct links to download Carrier, e.g. TE0706 REV02:

TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

Date format: YYYY-MM-DD
Example:
Date Revision Changes Documentation Link
2020-11-25 REV02
Resistors R14 and R15 was replaced by 953R (was 5K1)
Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
REV02

Hardware The hardware revision number can be found is on the PCB board together with adjacent to the module model number identifier, separated by the a dash.

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title	Board hardware revision number.

Scroll Ignore
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Date	Revision	Changes	PCN Link	Documentation Link
2023-10-01	Initial Revision			REV01 Documentation

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
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Date

Revision

Contributor

Description

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type	Flat

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infoType	Modified by
type	Flat
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<add TRM change list here>

01

Initial Release

--

all

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type	Flat
showVersions	false

--

Disclaimer

Include Page

	IN:Legal Notices
	IN:Legal Notices

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Trenz Electronic Documentation

Page History

Versions Compared

Old Version 8

New Version Current

Key

Overview

Key Features

Block Diagram

Main Components

Initial Delivery State

Initial Delivery State

Signals, Interfaces and Pins

Connectors

Signals, Interfaces and Pins

Connectors

Test Points

Test Points

On-board Peripherals

System Controller

FTDI FT2232H

FTDI FT230XQ

EEPROM

SD IO Port Expander

I2C Repeater

Oscillator

Configuration and System Control Signals

Power and Power-On Sequence

Power Rails

Recommended Power up Sequencing

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings *)

On-board Peripherals

System Controller

FTDI FT2232H

EEPROM

FTDI FT230XQ

Oscillator

SD IO Port Expander

Configuration and System Control Signals

Power and Power-On Sequence

Power Rails

Recommended Power up Sequencing

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings *)

Recommended Operating Conditions

Temperature Range:

Voltage Rails:

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

Disclaimer

Table of contents

Absolute Maximum Ratings ^*)

Absolute Maximum Ratings ^*)