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Features
- Single 3.3V input
- Header for TE0790 JTAG/UART Adapter
- 20 PIn ARM JTAG header (connected to MIO JTAG 0)
- 10 Pin I2C header for Silabs Clock Builder Field Programmer
- Done, Error/Status LEDs
- One PL GT with SMA connectors
- One PS GT with SMA connectors
- GT local loopback
- PL I/O loopbacks
- PS I/O loopbacks
- Boot Mode switches
- Power control switches to control TE0808 power domains
Recommended Accessories
TesKit is a "Test Fixture" for testing TE0808, most I/O pins are looped back for I/O Connector connectivity testing. For additional testing an LVDS oscillator is providing known clock to GT Reference Clock. SMA Connectors are provided on PL and on PS Connected GT lanes. Connector is provided for direct connection to SiLabs ClockBuilder Pro Field Programmer for Si5345 Programming.
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Supported Bootmodes are SPI and JTAG.
Getting Started
TestKits are pre-assembled and pre-flashed with initial Flash image, they start up as soon as power (3.3V) is applied.
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Power would be around 3W if the ZU+ does not boot (DDR4 not active). With Linux booted (or hello world from DDR4), the power consumption goes up to some 5W. If the junction temperature goes higher, then the power consumption goes up to 6-7W.
Startup procedure
- Connect mini-USB Cable to PC
- Start terminal 115200 Baud
- Connect 3.3V Supply to 2mm Banana Connectors
- Turn on power
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To restart the boot process press the small push-button on TE0790, it is wired to TE0808 Reset.
Manual test
TesKit808, mini-USB cable not connected, 3.3V power applied.
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| TE0790 SW | TE0808 RLED | TE0790 GLED | TE0790 RLED | DONE | ERR |
|---|---|---|---|---|---|
| Pressed | OFF | ON | ON | OFF | OFF |
| Released | OFF | ON | ON | ON | ON |
Function Description
GT transceiver have either internal connection or loopbacks or are connected to SMA Connectors. Note that connections to SMA are not AC Coupled!
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PL I/O has on-board internal loopback an all pins for connectivity testing.
UART
UART is available on MIO68, MIO69 via the supplied TE0790 USB Module. TE0808 and TE0803 board parts do not support this settings. They must be changed manually.
Boot Mode Settings
| M3 | M2 | M1 | M0 | Bootmode Hex | Bootmode | Notes |
|---|---|---|---|---|---|---|
| ON | ON | ON | ON | 0x0 | PS Main JTAG (TE0790 USB JTAG) | Needed for SPI Flash Programming |
| ON | ON | OFF | ON | 0x2 | SPI Flash (dual parallel, 4bit x 2, 32bit Addressing) | Default |
SPI Flash Programming
Flash programming is supported from SDK GUI, fsbl.elf that is needed is provided in common download area.
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| Note |
|---|
| NOTE: Boot mode must be set to JTAG before starting Flash Programming. |
See Xilinx AR66715
Reference and Test Designs
Please check Project Delivery - Xilinx AMD devices first.
Hello World
This works out of the box with Vivado/SDK 2016.1, if you only have EVAL license for ZU+ then it is necessary to export HDF without bitstream.
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| Note |
|---|
| NOTE: 2016.1 Bootgen seems to have small bug, automatically generated BIF file has bitstream partition set to PS as destination device what results in BOOT.BIN that does not load correctly. Make sure it is set to PL. This problem has been fixed in 2016.2 |
Petalinux
Support in Petalinux 2016.x for ZU+ MPSoC is fully integrated. Vivado HSI flow works, all settings from Vivado Design are imported to SDK and Petalinux to generate a working system with all required software components.
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Note: if there are no network drivers installed, then linux boot does stop on "Configuring network interfaces..." as workaround special "disable network" application can be installed into petalinux to allow booting with no network.
IBERT
If Si5345 is not programmed then there is only 1 GT Clock available, from 125MHz oscillator on TEBT0808, it does clock B228 CLK0 input, with this clock up to 12 GT can be tested, including the GT that has SMA connectors.
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IBERT with external Loopback on QUAD228, using 125MHz LVDS clock from TEBT0808 base.
Si5345 Programming
Setup for Si5345 PLL Programming using SiLabs ClockBuilder Pro Field Programmer.
References
- Silabs ClockBuilder Pro Field Programmer
- TEBT0808 Documentation
- TE0808 Documentation
- Xilinx Zynq UltraScale MPSoC Base TRD
Document Change History
| Date | Revision | Contributors | Description |
|---|---|---|---|
| 2017-06-07 | John Hartfiel | Initial version. |
Disclaimer
| Include Page | ||||
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