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Table of contents
Table of Contents |
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Zip Project Delivery
Zip Name Description
Description | PCB Name | Project Name+(opt. Variant) | supported VIVADO Version | Build Version and Date | ||||
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Example: | TE0726 | - | test_board_noprebuilt | - | vivado_2015.4 | - | build_26_20160415133543 | .zip |
Last supported Release
Type or File | Version |
---|---|
Vivado Design Suite | 2016.2 |
Trenz Project Scripts | 2016.2.01 |
Trenz <board_series>_board_files.csv | 1.2 |
Trenz apps_list.csv | 1.8 |
Trenz zip_ignore_list.csv | 1.0 |
Directory structure
File or Directory | Type | Description |
---|---|---|
<design_name> | base directory | Base directory with predefined batch files (*.cmd) to generate or open VIVADO-Project |
<design_name>/block_design/ | source | Script to generate Block Design in Vivado (*_bd.tcl). (optional) Some board part designs used subfolder <board_file_shortname> with Board Part specific Block Design (*_bd.tcl). |
<design_name>/board_files/ | source | Local board part files repository and a list of available board part files (<board_series>_board_files.csv) |
<design_name>/constraints/ | source | Project constrains (*.xdc). Some board part designs used subfolder <board_file_shortname> with additional constrains (*.xdc) |
<design_name>/doc/ | source | Documentation |
<design_name>/hdl/ | source | HDL-File and XCI-Files. Advanced usage only! |
<design_name>/firmware/ | source | ELF-File Location for MicroBlaze Firmware. Additional sub folder is used for MicroBlaze identification. |
<design_name>/ip_lib/ | source | Local Vivado IP repository |
<design_name>/misc/ | source | (Optional) Directory with additional sources |
<design_name>/prebuilt/boot_images/ | prebuilt | Directory with prebuilt boot images (*.bin) and configuration files (*.bif) for zynq and configured hardware files (*.bit and *.mcs) for micoblaze included in sub-folders: default or <board_file_shortname>/<app_name> |
<design_name>/prebuilt/hardware/ | prebuilt | Directory with prebuilt hardware sources (*.bit, *hdf, *.mcs) and reports included in subfolders: default or <board_file_shortname> |
<design_name>/prebuilt/software/ | prebuilt | (Optional) Directory with prebuilt software sources (*.elf) included in subfolders: default or <board_file_shortname>/<app_name> |
<design_name>/prebuilt/os/ | prebuilt | (Optional) Directory with predefined OS images included in subfolders <os_name>/<board_file_shortname> or <os_name>/default |
<design_name>/scripts/ | source | TCL scripts to build a project |
<design_name>/settings/ | source | (Optional) Additional design settings: zip_ignore_list.csv, vivado project settings, SDSOC settings |
<design_name>/software/ | source | (Optional) Directory with additional software |
<design_name>/os/ | source | (Optional) Directory with additional os sources in in subfolders <os_name> |
<design_name>/sw_lib/ | source | (Optional) Directory with local SDK/HSI software IP repository and a list of available software (apps_list.csv) |
<design_name>/v_log/ | generated | (Temporary) Directory with vivado log files (used only when Vivado is started with predefined command files (*.cmd) from base folder otherwise this logs will be writen into the vivado working directory) |
<design_name>/vivado/ | work, generated | (Temporary) Working directory where Vivado project is created. Vivado project file is <design_name>.xpr |
<design_name>/vivado_lab/ | work, generated | (Optional/Temporary) Working directory where Vivado LabTools is created. LabTools project file is <design_name>.lpr |
<design_name>/workspace/hsi | work, generated | (Optional/Temporary) Directory where hsi project is created |
<design_name>/workspace/sdk | work, generated | (Optional) Directory where sdk project is created |
<design_name>/sdsoc | work, generated | (Optional) Directory where SDSOC project is created |
<design_name>/backup/ | generated | (Optional) Directory for project backups |
Windows Command Files
File Name | Description |
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Design + Settings | |
design_basic_settings.cmd | Settings for the other *.cmd files. Following Settings are avaliable:
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design_clear_design_folders.cmd | (optional) Attention: Delete "<design_name>/v_log/", "<design_name>/vivado/", "<design_name>/vivado_lab/", "<design_name>/sdsoc/", and "<design_name>/workspace/" directory with related documents! |
design_run_project_batchmode.cmd | (optional) Create Project with setting from "design_basic_settings.cmd" and source folders. Build all Vivado hardware and software files if the sources are available. Delete "<design_name>/vivado/", and "<design_name>/workspace/hsi/" directory with related documents before Projekt will created. |
Hardware Design | |
vivado_create_project_guimode.cmd | Create Project with setting from "design_basic_settings.cmd" and source folders. Vivado GUI will be opened during the process. Delete "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Projekt will created. |
vivado_create_project_batchmode.cmd | (optional) Create Project with setting from "design_basic_settings.cmd" and source folders. Delete "<design_name>/vivado/", and "<design_name>/workspace/" directory with related documents before Projekt will created. |
vivado_open_existing_project_guimode.cmd | Opens an existing Project "<design_name>/vivado/<design_name>.xpr" and restore Script-Variables. |
Software Design | |
sdk_create_prebuilt_project_guimode.cmd | (optional) Create SDK project with hardware definition file from prebuild folder. It used the *.hdf from: <design_name>/prebuilt/hardware/<board_file_shortname>/. Set <board_file_shortname> and <app_name> in "design_basic_settings.cmd". |
Programming | |
program_flash_binfile.cmd | (optional) For Zynq Systems only. Programming Flash Memory via JTAG with specified Boot.bin. Used SDK Programmer (Same as SDK "Program Flash") or LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the boot.bin from: <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name>. Settings are done in "design_basic_settings.cmd". |
program_flash_mcsfile.cmd | (optional) For Non-Zynq Systems only. Programming Flash Memory via JTAG with specified <design_name>.mcs. Used LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the <design_name>.mcs from: <design_name>/prebuilt/hardware/<board_file_shortname>. Settings are done in "design_basic_settings.cmd". |
program_fpga_bitfile.cmd | (optional) Programming FPGA via JTAG with specified <design_name>.bit. Used LabTools Programmer (Vivado or LabTools only), depends on installion settings. Default, it used the <design_name>.bit from: <design_name>/prebuilt/hardware/<board_file_shortname>. Settings are done in "design_basic_settings.cmd". |
labtools_open_project_guimode.cmd | (optional) Create or open an existing Vivado Lab Tools Project. (Additional TCL functions from Programming and Utilities Group are usable). Settings are done in "design_basic_settings.cmd". |
TE-TCL-Extentsions
Name | Options | Description (Default Configuration) |
---|---|---|
TE::help | Display currently available functions. Important: Use only displayed functions and no functions from sub-namespaces | |
Hardware Design | ||
TE::hw_blockdesign_export_tcl | [-no_mig_contents] [-no_validate] [-mod_tcl] [-svntxt <arg>] [-board_part_only] [-help] | Export Block Design to project folder <design_name>/block_design/ . Old *bd.tcl will be overwritten! |
TE::hw_build_design | [-export_prebuilt] [-export_prebuilt_only] [-help] | Run Synthese, Implement, and generate Bit-file, optional MCS-file and some report files |
Software Design | ||
TE::sw_run_hsi | [-run_only] [-prebuilt_hdf <arg>] [-no_hsi] [-no_bif] [-no_bin] [-no_bitmcs] [-clear] [-help] | Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -prebuild_hdf <arg> isn't set.
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TE::sw_run_sdk | [-open_only] [-update_hdf_only] [-prebuilt_hdf <arg>] [-clear] [-help] | Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -prebuild_hdf <arg> isn't set. |
Programming | ||
TE::pr_init_hardware_manager | [-help] | Open Hardwaremanager, autoconnect target device and initialise flash memory with configuration from *_board_files.csv. |
TE::pr_program_jtag_bitfile | [-used_board <arg>] [-swapp <arg>] [-available_apps] [-used_basefolder_bitfile] [-help] | Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -used_board <arg> isn't set (Vivado only). (MicroBlaze only) If "-swapp" is set, the Bitfile with *.elf configuration is used from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name> |
TE::pr_program_flash_binfile | [-no_reboot] [-used_board <arg>] [-swapp <arg>] [-available_apps] [-force_hw_manager] [-used_basefolder_binfile] [-help] | Attention: For Zynq Systems only! |
TE::pr_program_flash_mcsfile | [-no_reboot] [-used_board <arg>] [-swapp <arg>] [-available_apps] [-used_basefolder_mcsfile] [-help] | Copies current Hardware files and reports from the vivado project to the prebuilt folder, if -used_board <arg> isn't set (Vivado only). (MicroBlaze only) If "-swapp" is set, the MCSfile with *.elf configuration is used from <design_name>/prebuilt/boot_images/<board_file_shortname>/<app_name> |
Utilities | ||
TE::util_zip_project | [-save_all] [-remove_prebuilt] [-manual_filename <arg>] [-help] | Make a Backup from your Project in <design_name>/backup/ Zip-Program Variable must be set in start_settings.cmd. Currently only 7-Zip is supported. |
Beta Test (Advanced usage only!) | ||
TE::ADV::beta_util_sdsoc_project | [-check_only] [-start_sdsoc_only] [-help] | Create SDSOC-Workspace. Currently only on some Reference-Designs available. Run [-check_only] option to check SDSOC ready state. |
TE::ADV::beta_hw_remove_board_part | [-permanent] [-help] | Reconfigure Vivado project as project without board part. Generate XDC-File from board part IO definitions and change ip board part properties. No all IPs are supported. |
TE::ADV::beta_hw_export_rtl_ip | \[-help\] | Save IPs used on rtl designs as *.xci in <design_name>hdl/xci. If sub folder <board_file_shortname> is defined this will be saved there. |
Design Environment: Usage
Reference-Design: Getting Started
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Basic Design Settings
Project Configuration
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- Select the correct Xilinx Program path (See: Windows Command Files → design_basic_settings.cmd)
- Select the correct board part number for your PCB (See: Windows Command Files → design_basic_settings.cmd)
- Other settings are optional (See: Windows Command Files → design_basic_settings.cmd)
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Initialise TE-scripts on Vivado/LabTools
- Variant 1 (recommended):
- Start the project with the predefined command file (vivado_open_existing_project_guimode.cmd) respectively LabTools with (labtools_open_project_guimode.cmd)
- Variant 2:
- Create your own Initialisation Button on the Vivado GUI:
- Tools → Customize Commands → Customize Commands...
- Push
- Type Name ex.: Init Scripts
- Press Enter
- Select Run command and insert:
- for Vivado: cd [get_property DIRECTORY [current_project]]; source -notrace "../scripts/reinitialise_all.tcl"
- for LabTool: cd [pwd]; source -notrace "../scripts/reinitialise_all.tcl"
- Press Enter
- A new Button is shown on the Vivado Gui: All Scripts are reinitialised, if you press this Button.
- Create your own Initialisation Button on the Vivado GUI:
- Variant 3:
- Reinitialise Script on Vivado TCL-Console:
- Type: source ../scripts/reinitialise_all.tcl
- Type: source ../scripts/reinitialise_all.tcl
- Reinitialise Script on Vivado TCL-Console:
Use predefined TE-Script functions
- Variant 1 (recommended):
- Typ function on Vivado TCL Console, ex.: TE::help
- TE::help
- Show all predefined TE-Script functions.
- TE:<functionname> -help
- Show short description of this function.
- Attention: If -help argument is set, all other args will be ignored.
- Variant 2:
- Create your own function Button on the Vivado GUI:
- Tools → Customize Commands → Customize Commands...
- Push +
- Type Name ex.: Run SDK
- Press Enter
- Select Run command and insert function:
- Variante 1 (no Vivado request window for args):
- insert function and used args, ex.: TE::sw_program_zynq -swapp hello_world
- Variant 2 (Vivado request window for args):
- insert function, ex.:TE::sw_program_zynq
- Press Define Args...
- For every arg:
- Push
- Typ Name, Comment, Default Value and set optional
- Press Enter
- Example for args:
- Push
- Index, Key Name, -swapp,
- Push
- Appname, Arg, hello_world,
- Variante 1 (no Vivado request window for args):
- Press Enter
- A new Button is shown on the Vivado Gui.
- Create your own function Button on the Vivado GUI:
Hardware Design
Block Design Conventions
- Only one Block-Design per project is supported
Recommended BD-Names (currently importend for some TE-Scripts):
Name Description zsys Idendify project as Zynq Project with processor system (longer name with *zsys* are supported too) zusys Idendify project as UltraScaleZynq Project with processor system (longer name with *zusys* are supported too) msys Idendify project as Microblaze Project with processor system (longer name with *msys* are supported too) fsys Idendify project as FPGA-fabric Project without processor system (longer name with *fsys* are supported too)
XDC Conventions
- All *.xdc from <design_name>/constrains/ are load into the vivado project on project creation.
Attention: If subfolder <design_name>/constrains/<board_file_shortname> is defined, it will be used the subfolder constrains only for this module! Recommended XDC-Names (used for Vivado XDC-options):
Property Name part Description Set Processing Order *_e_* set to early *_l_* set to late set to normal Set Used In *_s_* used in synthese only *_i_* used in implement only used in both, synthese and implement
Backup Block Design as TCL-File
- Backup your Block-Design with TCL-Command "TE::hw_blockdesign_export_tcl" in <design_name>/block_design/
It will be saved as *_bd.tcl
Attention: If subfolder <design_name>/block_design/<board_file_shortname> is defined, it will be saved there!
Only one *.tcl file shoud be in the backup folder respectively the subfolder <board_file_shortname>
Microblaze Firmeware
- Microblaze Firmware (*.elf) can be add to the source folder <design_name>/firmware/<Microblaze IP Instance>.
Software Design
HSI: Generate predefined software from libraries
- To generate predefinde software from libraries, run "TE::sw_run_hsi" on Vivado TCL-Console
- All programs in in <design_name>/sw_lib/apps_list.csv are generated automaticly
- Supported are local application libaries from <design_name>/sw_lib/sw_apps or the most Xilinx SDK Applications found in %XILDIR%/SDK/%VIVADO_VERSION%/data/embeddedsw/lib/sw_app
SDK: Create user software project
- To start SDK project, run "TE::sw_run_sdk" on Vivado TCL-Console
Include Hardware-Definition-File, Bit-file and local Software-libraries from <design_name>/sw_lib/sw_apps - To use Hardware-Definition-File, Bit-file from prebuilt folder without building the vivado hardware project, run "sdk_create_prebuilt_project_guimode.cmd" or type "TE::sw_run_sdk -prebuilt_hdf <board_number>" on Vivado-TCL-Console
- To open an existing SDK-project without update HDF-Data, type "TE::sw_run_sdk -open_only" on Vivado-TCL-Console
Advanced Usage
Attention not all features of the TE-Scripts are supported in the advanced usage!
User defined board part csv file
Name | Description | Value | |
---|---|---|---|
ID | ID to identify the board variant of the module series, used in TE-Scripts | Number, should be unique in csv list | |
PRODID | Product ID, currently not used in TE-Scripts | Product Name | |
PARTNAME | FPGA Part Name, used in Vivado and TE-Scripts | Part Name, which is available in Vivado, ex. xc7z045ffg900-2 | |
BOARDNAME | Board Part Name, used in Vivado and TE-Scripts | Board Part Name or "NA", which is available in Vivado, NA is not defined to run without boardpart, ex. trenz.biz:te0782-02-45:part0:1.0 | |
SHORTNAME | Subdirectory name, used for multi board projects to get correct sources and save prebuilt data | Name, should be unique in csv list | |
ZYNQFLASHTYP | Flash typ used for programming Zynq-Devices via SDK-Programming Tools (program_flash) | "qspi_single" or "NA", NA is not defined | |
FPGAFLASHTYP | Flash typ used for programming Devices via Vivado/LabTools | "<Flash Name from Vivado>|<SPI Interface>|<Flash Size in MB>" or "NA" , NA is not defined, ex. s25fl256s-3.3v-qspi-x4-single|SPIx4|32 Flash Name is used for programming, SPI Interface and Size in MB is used for *.mcs build. |
To modifiy current csv list, make a copy of the original csv and rename with suffix "_mod.csv", ex.TE0782_board_files.csv as TE0782_board_files_mod.csv. Scripts used modified csv instead of the original file.
User defined Settings
Vivado settings:
Vivado Project settings (corresponding TCL-Commands) can be saved as a user defined file "<design_name>/settings/project_settings.tcl". This file will be loaded automatically on project creation.
Script settings:
Additional script settings (only some predefined variables) can be saved as a user defined file "<design_name>/settings/development_settings.tcl". This file will be loaded automatically on script initialisation.
ZIP ignore list:
Files which should not be added in the backup file can be can be defined in this file: "<design_name>/settings/zip_ignore_list.tcl". This file will be loaded automaticaly on script initialisation.
SDSOC settings:
SDSOC settings will be disposited on the following files: "<design_name>/settings/<design_name>_pfm.tcl" and "<design_name>/settings/<design_name>_sw.pfm"
HDL-Design
HDL files can be saved in the subfolder "<design_name>/hdl/" or "<design_name>/hdl/<shortname>". They will be loaded automatically on project creation. Available formats are *.vhd, *.v and *.sv. A own top-file must be specified with the name "<design_name>_top.v" or "<design_name>_top.vhd".
To set file attributes, the name must include "_simonly_" for simulation only and "_synonly_" for synthese only.
RTL-IP-cores (*.xci). can be saved in the subfolder "<design_name>/hdl/xci" or "<design_name>/hdl/xci/<shortname>". They will be loaded automatically on project creation.
Checklist / Troubleshoot
- Are you using exactly the same Vivado version? If not then the scripts will not work, no need to try.
- Ary you using Vivado in Windows PC? Vivado works in Linux also, but the scripts are tested on Windows only.
- Is you PC OS Installation English? Vivado may work on national versions also, but there have been known problems.
- Are space character on the project path? Somtimes TCL-Scripts can't handle this correctly. Remove spaces from project path.
- Did you have the newest reference design build version? Maybe it's only a bug from a older version.
- Check <design_name>/v_log/vivado.log? If no logfile exist, wrong xilinx paths are set in design_basic_settings.cmd
- If nothing helps, send a mail to trenz support (support(at)trenz-electronic.de) with subject line "[TE-Reference Designs] ", the complete zip-name from your reference design and the last log file (<design_name>/v_log/vivado.log)
References
- Vivado Design Suite User Guide - Getting Started (UG910)
- Vivado Design Suite User Guide - Using the Vivado IDE (UG893)
- Zynq-7000 All Programmable SoC Software Developers Guide (UG821)
- SDSoC Environment User Guide - Getting Started (UG1028)
- SDSoC Environment - User Guide (UG1027)
- SDSoC Environment User Guide - Platforms and Libraries (UG1146)
Document Change History
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