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Traces of differential signals pairs are :
For applications where traces length has to be matched or timing differences have to be compensated, Table 42 and Table 43 list the trace length of I/O signal lines measured from FPGA balls to B2B connector pins.
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PUDC_B (pull-up during configuration, active Low) pin in TE0320 modules is hard-wired high, determining user-I/O pins to float before and during configuration. Turning off pull-up resistors in hot-swap or hot-insertion applications, disables potential current paths to the I/O power rail. However, external pull-up or pull-down resistors may be required on each individual I/O pin depending on the specific application.