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Getting this Design ported to any new board usually takes less than 5 minutes. So far all newly ported design for new boards have worked first time tested with 0 time wasted in debug or troubleshooting.
Ready to use project and bitstreams are available from the LED Blinky Tutorial.
F32C Core
This is work to convert F32C into fully usable IP Catalog Processor IP Core.
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Setting F32C BRAM size in Vivado IPI Address Editor.
Problem: it is not possible to assign an ELF files to the BRAM that we add in such way not directly in Vivado IPI. As workaround several options exist, we can create an BOOTROM IP Core that can be connected to the LMB Bus holding the bootcode or we can create a BOOSTRAP IP Core that writes the bootrom code into the main BRAM and then releases F32C reset. Of course it is possible to merge the ELF into bitstream with console commands or TCL scripting.
LMB Bootrom IP Core added with fixed code for the bootstrap.
Debug session in Vivado Labtools, when CPU Reset is asserted Instruction address bus freezes, but after release there seems to be no reset, F32C Core tries to continue from last PC Address.
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