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| Pin Name | Mode | Function | Default Configuration |
|---|---|---|---|
| PGOOD | Output | Power good | Active high when all on-module power supplies are working properlyPower Good Pin is zero, if RESIN, EN1, PG_SENSE or PG_DDR_PWR are low, else high impedance. EN1 is also used to enable 1V Power (connected directly outside of the CPLD). |
| JTAGEN | Input | JTAG select | Low for normal operation, high for System Controller CPLD access. |
| EN1 | Input | Power Enable | When forced low, pulls PROG_B low to emulate power on reset. |
| RESIN | When forced low, pulls PROG POR_B low to emulate power on reset. | ||
| NOSEQ | - | No function | Not used. |
| MODE | - | No function | Not used. |
Note: Pin functionality depends on the running CPLD Firmware, newest one is described here TE0713 CPLD
On-board LEDs
The TE0713-01 module has one LED which is connected to the System Controller CPLD. Once FPGA configuration has completed, it can be used by the user's design.
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On-board Si5338 clock generator chip is used to generate clocks with 25 MHz oscillator connected to the pin IN3 as input reference. There is a I2C bus connection between the FPGA bank 14 (master) and clock generator chip (slave) which can be used to program output frequencies. See the reference design for more information.
| CLK Output | FPGA Bank | FPGA Pin | IO Standard | Net Name | Default Freq | Note |
|---|---|---|---|---|---|---|
| CLK0 | - | - | - | - | -- | N.C. |
| CLK1 | - | - | - | - | -- | N.C. |
| CLK2 | 216 | F6/E6 | Auto | MGT_CLK0_P/N | 125 MHz | GTP transceiver clock. |
| CLK3 | 35 | H4/G4 | LVDS | PLL_CLK_P/N | 200 MHz | AC coupled, board termination |
On-board Peripherals
32 MByte Quad SPI Flash Memory
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System Controller CPLD (Lattice Semiconductor MachXO2-256HC, U3) is used to control FPGA configuration process. The FPGA is held in reset (by driving the PROG_B signal low) until all power supplies have stabilized.
By driving signal RESIN to low you can reset the FPGA. This signal can be driven from the user’s baseboard PCB via the B2B connector JM2 pin 18.
Input EN1 is also gated to FPGA reset, should be open or pulled up for normal operation. By driving EN1 low, on-board DC-DC converters will be not turned off.
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CPLD Firmware description:
DDR3L SDRAM
The TE0713-01 SoM has two 4 Gbit volatile DDR3 SDRAM ICs (U15 and U19) for storing user application code and data.
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TE0713-01 is equipped with the FTDI FT600Q high performance USB 3.0-to-FIFO interface bridge chip.
FTDI doesn't support 245 Synchronous FIFO mode on TE0713, please use FT60X Chip Configuration Programmer to change Mode into “Multi-Channel FIFO mode”.
| Info |
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SSTX_P and SSTX_N ar swapped on the PCB,this will be corrected automatically on link training on USB3 |
Power and Power-On Sequence
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Date | Revision | Contributors | Description | ||||||||||||||||||||||
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| 2019-07-03 | v.13 | John Hartfiel |
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| 2018-10-24 | v.11 | John Hartfiel |
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2018-09-19 | v.9 | John Hartfiel |
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2018-06-07 | v.8 | John Hartfiel |
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| 2017-05-28 | v.6 | Jan Kumann |
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| 2017-02-07 | v.1 | Jan Kumann |
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| -- | all |
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Disclaimer
| Include Page | ||||
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Overview
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