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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
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Key Features
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Revision History
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Release Notes and Know Issues
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Requirements
Software
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
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Design supports following carriers:
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*used as reference |
Additional HW Requirements:
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*used as reference |
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For general structure and of the reference design, see Project Delivery - Xilinx AMD devices
Design Sources
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Prebuilt
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Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
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Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- AMD Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):
- Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") TE::hw_build_design -export_prebuilt
Info Using Vivado GUI is the same, except file export to prebuilt folder.
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Generate Programming Files with Vitis
- Copy PetaLinux
- build image files to prebuilt folder
- copy u-boot.elf,
- system.dtb,
- bl31.
- elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
Info "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>" Page properties hidden true id Comments This step depends on Xilinx Device/Hardware
for Zynq-7000 series
- copy u-boot.elf, u-boot.dtb, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ZynqMP
- copy u-boot.elf, u-boot.dtb, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for Microblaze
- ...
- elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
Generate Programming Files
Code Block language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)
Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
- Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart
Launch
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Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash) TE::pr_program_flash -swapp u-boot TE::pr_program_flash -swapp hello_te0802 (optional)
Note To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup
- Copy image.ub and boot.scr on SD or USB
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to QSPI-Boot and insert SD or USB.
- Depends on Carrier, see carrier TRM.
SD-Boot mode
- Copy image.ub, boot.scr and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Connect Monitors, ETH, M2...
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Info Note: See TRM of the Carrier, which is used.
Tip Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
The boot options described above describe the common boot processes for this hardware; other boot options are possible.
For more information see Distro Boot with Boot.scrPower On PCB
Expand title boot process 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
Page properties hidden true id Comments This step depends on Xilinx Device/Hardware
for Zynq-7000 series
1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for ZynqMP???
1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,
3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for Microblaze with Linux
1. FPGA Loads Bitfile from Flash,
2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available)
3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),
4. U-boot loads Linux from QSPI Flash into DDR
for native FPGA
...
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
select COM Port
Info Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Code Block language bash theme Midnight # password default disabled with 2021.2 petalinux release petalinux login: root Password: root
Info Note: Wait until Linux boot finished
You can use Linux shell now.
Code Block language bash theme Midnight I2C i2cdetect -l (Shows a list of the available I2C buses) i2cdetect -y -r 0 (check I2C 0 Bus) RTC dmesg | grep rtc (RTC check) ETH0 udhcpc (ETH0 check) USB lsusb (USB check) PCIe (M2 SSD) lspci (PCIe check) Audio aplay /<link to mounted sd card>/<filename>.wav (e.g. aplay /run/mount/sd/<filename>.wav) Note: Display Port must be connected to activate audio drivers. Use .wav or other aplay supported formate VGA connect VGA to monitor and adjust source (it shows test pattern) Display port second console will be shown on the monitor, when boot process is finished. Note: connect keyboard to TE0802 USB, to interact with the second console petalinux login: root Password: root
Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")
- Webserver to get access to Zynq
- All button cross will be reset LEDs with values from DIP
- LCD is connected to counter
Vivado HW Manager
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- 25MHz CLK Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
- 25MHz CLK Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
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System Design - Vivado
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PS Interfaces
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Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
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set_property PACKAGE_PIN E3 [get_ports PWM_L] set_property PACKAGE_PIN F4 [get_ports PWM_R] set_property IOSTANDARD LVCMOS18 [get_ports PWM_*] set_property PACKAGE_PIN P3 [get_ports {USER_SW[0]}] set_property PACKAGE_PIN P2 [get_ports {USER_SW[1]}] set_property PACKAGE_PIN M1 [get_ports {USER_SW[2]}] set_property PACKAGE_PIN L1 [get_ports {USER_SW[3]}] set_property PACKAGE_PIN K1 [get_ports {USER_SW[4]}] set_property PACKAGE_PIN J2 [get_ports {USER_SW[5]}] set_property PACKAGE_PIN M4 [get_ports {USER_SW[6]}] set_property PACKAGE_PIN M5 [get_ports {USER_SW[7]}] set_property IOSTANDARD LVCMOS18 [get_ports USER_SW*] set_property PACKAGE_PIN U2 [get_ports {USER_BTN_UP}] set_property PACKAGE_PIN U1 [get_ports {USER_BTN_RIGHT}] set_property PACKAGE_PIN T2 [get_ports {USER_BTN_DOWN}] set_property PACKAGE_PIN R1 [get_ports {USER_BTN_LEFT}] set_property PACKAGE_PIN T1 [get_ports {USER_BTN_OK}] set_property IOSTANDARD LVCMOS18 [get_ports USER_BTN*] set_property PACKAGE_PIN P1 [get_ports {LED[0]}] set_property PACKAGE_PIN N2 [get_ports {LED[1]}] set_property PACKAGE_PIN M2 [get_ports {LED[2]}] set_property PACKAGE_PIN L2 [get_ports {LED[3]}] set_property PACKAGE_PIN J1 [get_ports {LED[4]}] set_property PACKAGE_PIN H2 [get_ports {LED[5]}] set_property PACKAGE_PIN L4 [get_ports {LED[6]}] set_property PACKAGE_PIN L3 [get_ports {LED[7]}] set_property IOSTANDARD LVCMOS18 [get_ports LED*] set_property PACKAGE_PIN F2 [get_ports {VGA_R[0]}] set_property PACKAGE_PIN F1 [get_ports {VGA_R[1]}] set_property PACKAGE_PIN G2 [get_ports {VGA_R[2]}] set_property PACKAGE_PIN G1 [get_ports {VGA_R[3]}] set_property PACKAGE_PIN C2 [get_ports {VGA_G[0]}] set_property PACKAGE_PIN D2 [get_ports {VGA_G[1]}] set_property PACKAGE_PIN D1 [get_ports {VGA_G[2]}] set_property PACKAGE_PIN E1 [get_ports {VGA_G[3]}] set_property PACKAGE_PIN A3 [get_ports {VGA_B[0]}] set_property PACKAGE_PIN A2 [get_ports {VGA_B[1]}] set_property PACKAGE_PIN B2 [get_ports {VGA_B[2]}] set_property PACKAGE_PIN B1 [get_ports {VGA_B[3]}] set_property PACKAGE_PIN B7 [get_ports {VGA_VS[0]}] set_property PACKAGE_PIN A6 [get_ports {VGA_HS[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_B[3]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_B[2]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_B[1]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_B[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_G[3]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_G[2]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_G[1]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_G[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {VGA_HS[0]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_R[3]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_R[2]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_R[1]}] set_property IOSTANDARD LVCMOS18 [get_ports {VGA_R[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {VGA_VS[0]}] set_property PACKAGE_PIN J3 [get_ports CLK_25MHZ] set_property IOSTANDARD LVCMOS18 [get_ports CLK_25MHZ] # SEG_C[0] = SEG_CA set_property PACKAGE_PIN E4 [get_ports {SEG_C[0]}] set_property PACKAGE_PIN D3 [get_ports {SEG_C[1]}] set_property PACKAGE_PIN N5 [get_ports {SEG_C[2]}] set_property PACKAGE_PIN P5 [get_ports {SEG_C[3]}] set_property PACKAGE_PIN N4 [get_ports {SEG_C[4]}] set_property PACKAGE_PIN C3 [get_ports {SEG_C[5]}] set_property PACKAGE_PIN N3 [get_ports {SEG_C[7]}] set_property PACKAGE_PIN R5 [get_ports {SEG_C[6]}] set_property IOSTANDARD LVCMOS18 [get_ports SEG_C*] set_property PACKAGE_PIN A8 [get_ports {SEG_AN[0]}] set_property PACKAGE_PIN A9 [get_ports {SEG_AN[1]}] set_property PACKAGE_PIN B9 [get_ports {SEG_AN[2]}] set_property PACKAGE_PIN A7 [get_ports {SEG_AN[3]}] set_property PACKAGE_PIN B6 [get_ports {SEG_AN[4]}] set_property IOSTANDARD LVCMOS33 [get_ports SEG_AN*] |
Software Design - Vitis
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Application
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---------------------------------------------------------- FPGA Example ---------------------------------------------------------- scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 20212022.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 20212022.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: fsbl---------------------------------------------------------- fsblTE modified 2022TE modified 2021.2 FSBL General:
Module Specific:
fsbl_flashTE modified 2021.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2021.2 FSBL General: ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2021.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashpmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: TE modified 2021.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
zynqmp_fsbl
TE modified 20212022.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_
fsbl_flashpmufw
Xilinx default PMU firmware.
hello_te0802
Hello TE0802 is a Xilinx Hello
TE modified 2021.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
Xilinx default PMU firmware.
hello_te0802
Hello TE0802 is a Xilinx Hello World example as endless loop instead of one console output.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- generate u-boot.dtb:
- CONFIG_SUBSYSTEM_UBOOT_EXT_DTB=y
- add new flash partition for bootscr and sizing
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x1500000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x15000000x40000
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
- CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x40000
U-Boot
- Identification
- CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
- CONFIG_SUBSYSTEM_PRODUCT="TE0802"
U-Boot
Start with petalinux-config -Start with petalinux-config -c u-boot
Changes:
- MAC from eeprom together with uboot and device tree settings:
- CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFACONFIG_ENV_OVERWRITE=y
- CONFIG_SYSZYNQ_MAC_I2CIN_EEPROM _ADDR=0x50is not set
- CONFIG_SYSNET_I2C_EEPROM_BUS=1RANDOM_ETHADDR is not set
- Boot Modes:
- CONFIG_QSPI_BOOT=y
- CONFIG_SD_BOOT=y
- CONFIG_ENV_IS_IN_FAT is not set
- CONFIG_ENV_IS_IN_NAND is not set
- CONFIG_ENV_IS_IN_SPI_FLASH is not set
- CONFIG_SYS_REDUNDAND_ENVIRONMENT is not set
- CONFIG_BOOT_SCRIPT_OFFSET=0x1F40000
Change platform-top.h:
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Device Tree
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title | project-spec\meta-user\recipes-bsp\device-tree\files\system-user.dtsi |
- Identification
- CONFIG_IDENT_STRING=" TE0802"
Change platform-top.h:
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Device Tree
flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /*------------------ I2C --------------------*/ &i2c1 { eeprom: eeprom@50 { compatible = "microchip,24aa025", "atmel,24c02"; reg = <0x50>; #address-cells = <1>; #size-cells = <1>; eth0_addr: eth-mac-addr@FA { reg = <0xFA 0x06>; }; }; };Code Block | ||||
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/include/ "system-conf.dtsi" /*------------------ gtr --------------------*/ //https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver / { refclk2:psgtr_dp_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <27000000>; }; refclk1:psgtr_usb_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <26000000>; }; refclk0:psgtr_pcie_clock { compatible = "fixed-clock"; #clock-cells = <0x00>; clock-frequency = <100000000>; }; //refclk1:psgtr_sata_clock { // compatible = "fixed-clock"; // #clock-cells = <0x00>; // clock-frequency = <150000000>; //}; //refclk0:psgtr_unused_clock { // compatible = "fixed-clock"; // #clock-cells = <0x00>; // clock-frequency = <100000000>; //}; }; &psgtr { clocks = <&refclk0 &refclk1 &refclk2>; /* ref clk instances used per lane */ clock-names = "ref0\0ref1\0ref2"; }; /*------------------ SD --------------------*/ &sdhci0 { disable-wp; no-1-8-v; }; /*------------------ USB --------------------*/ &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; phy-names = "usb2-phy","usb3-phy"; maximum-speed = "super-speed"; }; /*------------------ LEDs --------------------*/ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/leds/common.h> / { leds { compatible = "gpio-leds"; ndp_en { label = "ndp_en"; gpios = <&gpio 26 GPIO_ACTIVE_HIGH>; default-state = "on"; }; ssd_sleep { label = "ssd_sleep"; gpios = <&gpio 32 GPIO_ACTIVE_HIGH>; default-state = "on"; }; usb_reset { label = "usb_reset"; gpios = <&gpio 38 GPIO_ACTIVE_HIGH>; default-state = "on"; }; }; }; /*------------------ ETH PHY --------------------*/ &gem3 { phy-handle = <&phy0>; nvmem-cells = <ð0_addr>; nvmem-cell-names = "mac-address"; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /*------------------ QSPI --------------------*/ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /*------------------ I2C --------------------*/ &i2c1 { eeprom: eeprom@50 { compatible = "microchip,24aa025", "atmel,24c02"; reg = <0x50>; #address-cells = <1>; #size-cells = <1>; eth0_addr: eth-mac-addr@FA { reg = <0xFA 0x06>; }; }; }; |
Kernel
Start with petalinux-config -c kernel
Changes:
- Only needed to fix JTAG Debug issue:
- # CONFIG_CPU_IDLE is not set
- # CONFIG_CPU_FREQ is not set
- CONFIG_EDAC_CORTEX_ARM64=yFREQ is not set
- Support PCIe memory card
- CONFIG_NVME_CORE=y
- CONFIG_BLK_DEV_NVME=y
- # CONFIG_NVME_MULTIPATH is not set
- # CONFIG_NVME_HWMON is not set
- # CONFIG_NVME_TCP is not set
- CONFIG_NVME_TARGET=y
- # CONFIG_NVME_TARGET_PASSTHRU is not set
- # CONFIG_NVME_TARGET_LOOP is not set
- # CONFIG_NVME_TARGET_FC is not set
- # CONFIG_NVME_TARGET_TCP is not set
- CONFIG_SATA_AHCI=y
- CONFIG_SATA_MOBILE_LPM_POLICY=0
- CONFIG_NVM=y
- CONFIG_NVM_PBLK=y
- CONFIG_NVM_PBLK_DEBUG=y
Rootfs
Start with petalinux-config -c rootfs
Changes:
- For web server app:
- CONFIG_busybox-httpd=y
- For additional test tools only:
- CONFIG_i2c-tools=y
- CONFIG_packagegroup-petalinux-utils=y (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
- For audio application
- CONFIG_alsa-utils=y
- CONFIG_alsa-utils-aplay=y
- For auto login:
- CONFIG_auto-login=y
- CONFIG_ADD_EXTRA_USERS="root:root;petalinux:;"
FSBL patch (alternative for vitis fsbl trenz patch)
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"
Applications
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
startup
Script App to load init.sh from SD Card if available.
webfwu
Webserver application suitable for Zynq access. Need busybox-httpd
Additional Software
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No additional software is needed.
Appx. A: Change History and Legal Notices
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Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
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