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titlePrebuilt files (only on ZIP with prebult content)

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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File

MCS-File

*.mcs

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

MMI-File

*.mmi

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

SREC-File

*.srec

Converted Software Application for MicroBlaze Processor Systems


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  1. Connect JTAG and power on PCB
  2. (if not done) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd" or open with "vivado_open_project_guimode.cmd", if generated.
  3. Type on Vivado Console: TE::pr_program_flash _mcsfile -swapp u-boot
    Note: Alternative use SDK or setup Flash on Vivado manually
              optional "TE::pr_program_flash_binfile -swapp hello_te0712" possible
  4. Reboot (if not done automatically)

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titleDocument change history.

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DateDocument RevisionAuthorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
current-version
current-version
prefixv.

Page info
infoTypeModified by
typeFlat

  • typo correction
2020-03-25c.35John Hartfiel
  • update scripts
2020-01-21v.34John Hartfiel
  • update scripts, new features and linux support
2020-01-08v.33John Hartfiel
  • 2019.2 release
2019-04-18v.32John Hartfiel
  • small design changes
2019-02-22

v.31

John Hartfiel
  • 2018.3 release (include design reworks)

2018-09-06

v.30John Hartfiel
  • 2018.2 release

2018-05-25

v.28John Hartfiel
  • Design update

2018-05-08

v.27John Hartfiel
  • Know Issues
  • Documentation

2018-04-12

v.23John Hartfiel
  • Design Update

2018-03-28

v.22John Hartfiel
  • Know Issue for PCB REV01 only
  • Fix typo
  • New assembly variant
2018-02-13v.19John Hartfiel
  • Release 2017.4
2018-01-08v.16John Hartfiel
  • Add SCU source path
2017-12-15v.15John Hartfiel
  • Update Design and Description
2017-11-07v.11John Hartfiel
  • Update Design Files
2017-10-06v.10John Hartfiel
  • small Document Update
2017-10-05

v.8

John Hartfiel
  • Release 2017.2
2017-09-11v.1

Page info
created-user
created-user

  • Initial release
---All

Page info
modified-users
modified-users

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