1. Added a VRP resistor on bank 65;
2. LDO U33 is changed on ADP7102ACPZ;
3. Signal FPGA IO0 is connected on AE18 pin of FPGA;
4. Signal DBG_LED3 is connected on AD18 pin of FPGA;
5. Signal MIO13_25 connected to J1 pin 33 instead MIO25.
6. Resistor R84 is removed;
7. LED D1 moved on edge of PCB;
8. Added THT testpoints J4 on CPLD_JTAGEN, R76 was removed;
9. Signals B49_XX_X are renamed in B88_XX_X;
10. C241 is changed on 1nF;
11. Length of CLK signals on RFADC and RFDAC are adjusted;
12. Wrong connection on U8 is fixed (PCB);
13. Wrong connection PGOOD1 pin of U7 is fixed;
Method of Identification
The revision number is printed in the top side of the PCB.