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Scroll pdf title
titlePower-on reset with fixed delay time of 200 ms
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After this delay, the /RESET line is reset high and the FPGA configuration can start.

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titleReset assertion on power drop with fixed delay time of 200 ms.
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Power-on Reset

TE0320 integrates a power-fail comparator which can be used for low-battery detection, power-fail warning, or for monitoring Vsup power rail.

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