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TE0630 is provided with a slide Dip switch S1B.
Slide Dip switch S1B conditions the value of signal PS_EN.
In this way, S1B conditionally/unconditionally enables the 1.2 V, 1.5 V and 2.5 V power rails. 
Figure 33: Slide Dip switch S1B (angle view).
Figure 34: Slide Dip switch S1B schematic.
Figure 35: When slide Dip switch S1B = FX2 PON, signal PS_EN is set to signal FX2_PS_EN driven by the EZ-USB FX2LP USB FX2 microcontroller under user control.
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S1B position | Default position | Effect on 1.2 V, 1.5 V and 2.5 V rails |
|---|---|---|
FX2 PON (off) |  | 1.2 V and 2.5 V rails controlled by USB FX2 microcontroller (signal FX2_PS_EN) PS_EN = FX2_PS_EN = 1 or 0 |
PON (on) |  | 1.2 V and 2.5 V rails always enabled (PS_EN = 1) PS_EN ≠ FX_PS_EN = 1 or 0 |
Table 14: Slide Dip switch S1B settings overview (1.2 V and 2.5 V rails only).
Signal FX2_PS_EN
To command signal FX2_PS_EN, read the reference firmware code.
IOD = 0x03; // Enable PS_EN and disable PROG_B
OED = 0x03; // Configure PS_EN and PROG as outputs
Port D Pin | Alternate Function | Alternate Function is Selected By... | Alternate Function is Described in... |
|---|---|---|---|
| PD.7:0 | FD[15:8] | IFCFG1 = 1 and any WORDWIIDE bit = 1 | Slave FIFOs chapter 9 on page 99 |
Table from EZ-USB(R) Technical Reference Manual (EZ-USB_TRM.pdf).
Signal PS_EN
- Signal PS_EN enables (1) or disables (0) power rails 2.5V and 1.2V.
Figure 36: Power rails 2.5V and 1.2V could be enabled/disabled by signal PS_EN. Power-rail 3.3V is not controlled by signal PS_EN and is unconditionally enabled.
Figure 37: Power rails 3.3V could not be enabled/disabled by signal PS_EN.
VCCIO assembly options
According to the corresponding assembly option, power rail VCCCIO0 can depend or not on the 2.5V power rail.
Figure 37: example of VCCIO0 assembly not dependent on 2.5V power rail. The other way is also possible.
SlideDip Switch S1B = FX2 PON
When slide Dip switch S1B is in the left position ( = FX2 PON : power rails conditionally on depending on signal FX2_PS_EN), signal PS_EN is set to signal FX2_PS_EN (PS_EN = FX2_PS_EN) driven by the EZ-USB FX2LP USB FX2 microcontroller under user control (IOD and OED of fw.c).
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- FPGA core logic (1.2V)
- DDR SDRAM (2.5V)
- FPGA bank 3 (2.5V)
- VREF (2.5V)
- VCCCIO0 (2.5V) FPGA bank 0 (if R131+R132- assembly)
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Dip Switch S1B = PON
Full power operation (PS_EN = 1): when slide Dip switch S1B is in the right position (PON = power rails unconditionally on), signal PS_EN is set to power rail 3.3V. Thus power rails 2.5V and 1.2V are unconditionally enabled.
Figure 39: S1B on position PON (PS_EN ≠ FX2_PS_EN = x; PS_EN = high ).
Summary table
Table 14 summarizes all switching options implied by slide Dip switch S1B and firmware signal FX2_PS_EN (under the standard assembly option).
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(2) R131 unsoldered / R132 soldered
Table 40: Slide Dip switch S1B settings overview ( 1.2V , 2.5V, VCCIO0).
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Slide Dip switch S1B can be replaced by one resistors in the following cases:
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Assembly option when resistor R17 not populated and R19 populated is equivalent to slide Dip switch S1B permanently set to PON.
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Assembly option when resistor R17 populated and R19 not populated is equivalent to slide Dip switch S1B permanently set to FX2 PON.
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Overview
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