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Port D Pin
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PD.7:0FD[15:8]

IFCFG1 = 1 and

any WORDWIIDE bit = 1
Slave FIFOs chapter 9 on page 99

Table from EZ-USB(R) Technical Reference Manual (EZ-USB_TRM.pdf).

Signal PS_EN

  • Signal PS_EN enables (1) or disables (0) power rails 2.5V and 1.2V.


    Figure 36: Power rails 2.5V and 1.2V could be enabled/disabled by signal PS_EN.

  • Power-rail 3.3V is not controlled by signal PS_EN and is unconditionally enabled. 
      
    Figure 37: Power rails 3.3V could not be enabled/disabled by signal PS_EN.
     

    The 3.3 V power-rail though is out of the control of the USB-microcontroller and is supplied down-converting the 5 V power supply provided by either the USB-bus or the B2B receptacle connector. In this case, signals that are applied to the 3.3 V I/O banks do not need to be disconnected when power-rails are disabled by the USB microcontroller.

     

VCCIO0 assembly options

According to the corresponding assembly option, power rail VCCCIO0 can depend or not on the 2.5V power rail.

Voltage VccIO for bank B0 shall span from 1.2 V to 3.3 V. VccIO can be supplied either externally or internally to the micromodule.

(warning)Warning! Spartan-3 I/Os are not 5 V tolerant. Applying more than the recommended operating voltages at any pin, results in a damaged FPGA (see Xilinx Answer AR#19146).

Externally Supplied VCCIO

 VccIO can be externally supplied over the B2B connector J4. If bank B0 is not used, then VccIO can be left open.

Internally Supplied VCCIO

If VccIO is not externally supplied, it can be internally supplied by one of the internal power rails of 2.5 V and 3.3 V. This is possible by short-circuiting one of the two pad pairs placed on the right of connector J4 at the top right corner of the bottom side of the micromodule.

Two suitable ways of shirt-circuiting the paid pair are by means of a zero-ohm 0603 (1608 metric) chip resistor or a solder blob.

 

Figure 37: example of VCCIO0 assembly. The soldering of R102 and R103 are mutually exclusive.


Figure 9 shows how to short-circuit VccIO to internal 3.3 V power rail. FX2_PS_EN does not control VCCCIO0 (3.3V) FPGA bank 0


Figure 10 shows how to short-circuit VccIO to internal 2.5 V power rail. FX2_PS_EN does control VCCCIO0 (2.5V) FPGA bank 0

Slide Switch S3 = FX2 PON 

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