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TE0320 can be power supplied in two ways:
- through USB connector J1,
- through B2B connector JM5 (pins 1 to 4).
The power supply source is determined by assembly option. See Figure 5the figure below.
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Any other assembly combination of R9, R11 and R12 is not allowed. |
On Board
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Power Rails
According to the Xilinx Spartan-3A DSP literature, there are the following power supply pin types:
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Table 1: On-board power rails summary.
Power Supervision
Power-on Reset
During power-on, the /RESET line is first asserted. Thereafter, the supply voltage supervisor monitors the power supply rail 3.3V and keeps the /RESET line active (low) as long as the rail remains below the threshold voltage (2.93 V). An internal timer delays the return of the /RESET line to the inactive state (high) to ensure proper system reset. The delay time of 200 ms starts after the rail has risen above the threshold voltage.
Figure 13: Power-on reset with fixed delay time of 200 ms.
After this delay, the /RESET line is reset high and the FPGA configuration can start.
When the rail voltage drops below the threshold voltage, the /RESET line becomes active (low) again.
Figure 14: Reset assertion on power drop with fixed delay time of 200 ms.
Overview
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