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Power Supervision
Power-on Reset
During power-on, the /RESET line is first asserted. Thereafter, the supply voltage supervisor monitors the power supply rail 3.3V and keeps the /RESET line active (low) as long as the rail remains below the threshold voltage (2.93 V). An internal timer delays the return of the /RESET line to the inactive state (high) to ensure proper system reset. The delay time of 200 ms starts after the rail has risen above the threshold voltage.
Figure 13: Power-on reset with fixed delay time of 200 ms.
After this delay, the /RESET line is reset high and the FPGA configuration can start.
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When the rail voltage drops below the threshold voltage, the /RESET line becomes active (low) again.
Figure 14: Reset assertion on power drop with fixed delay time of 200 ms.
Power Fail
TE0320 integrates a power-fail comparator which can be used for low-battery detection, power-fail warning, or for monitoring Vsup power rail.
An additional power-fail circuit can be used, to monitor the input voltage. At 4.4V, a power-fail signal (/PFO) is sent to the FPGA. Should you wish or need another threshold voltage, please contact Trenz Electronic.
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