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Figure 13: Power-on reset with fixed delay time of 200 ms.
After this delay, the /RESET line is reset high and the FPGA configuration can start.
When the rail voltage drops below the threshold voltage, the /RESET line becomes active (low) again.
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Power Fail
TE0320 integrates a power-fail comparator which can be used for low-battery detection, power-fail warning, or for monitoring Vsup power rail.
An additional power-fail circuit can be used, to monitor the input voltage. At 4.4V, a power-fail signal (/PFO) is sent to the FPGA. Should you wish or need another threshold voltage, please contact Trenz Electronic.
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