Page History
...
During power-on, the /RESET line is first asserted. Thereafter, the supply voltage supervisor monitors the power supply rail 3.3V and keeps the /RESET line active (low) as long as the rail remains below the threshold voltage (2.93 V). An internal timer delays the return of the /RESET line to the inactive state (high) to ensure proper system reset. The delay time of 200 ms starts after the rail has risen above the threshold voltage.
...
| Scroll pdf title | ||
|---|---|---|
|
...
After this delay, the /RESET line is reset high and the FPGA configuration can start.
...
Overview
Content Tools