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type
colour code

description

I/O

Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form differential I/Os.

Dual-purpose pin used in some configuration modes during the configuration process and then usually available as a user I/O after configuration. If the pin is not used during configuration, this pin behaves as an I/O-type pin. See Xilinx UG332: Spartan-3 Generation Configuration User Guide for additional information on these signals.

VREF

VREF0 provides a reference voltage input for certain I/O standards. See paragraph 6.9 Voltage Reference VREF0 for additional information on this signal.

CLK

Either a user-I/O pin or an input to a specific clock buffer driver. Packages have 16 global clock inputs that optionally clock the entire device. See the Using Global Clock Resources chapter in UG331: Spartan-3 Generation FPGA User Guide for additional information on these signals.

Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every package has two dedicated configuration pins. These pins are powered by VCCAUX. See Xilinx UG332: Spartan-3 Generation Configuration User Guide for additional information on these signals.

Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated pin and is powered by VCCAUX. AWAKE is a Dual-Purpose pin. Unless Suspend mode is enabled in the application, AWAKE is available as a user-I/O pin.

Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has four dedicated JTAG pins. These pins are powered by VCCAUX.

Dedicated ground pin. All must be connected.

TE

Trenz Electronic specific pin type. See the description of each pin in the user manual for additional information on the corresponding signals.