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The module has a 24 MHz SMD clock oscillator providing a clock source for both the EZ-USB FX2LP USB FX2 microcontroller (XTALIN) and the FPGA as detailed in the table below.

 

Scroll pdf title
title24 MHz clock signal details.

signal

FPGA pin

FPGA ball

FPGA bank

24MHZ1

IO_L28N_2
GCLK3

AE14

2

Digital Clock Manager (DCM)

The DCMs of the FPGA can be used to synthesize arbitrary clock frequencies from any on-board clock network, differential clock input pair or single-ended clock input. For further reference, please read Xilinx DS485:Digital Clock Manager (DCM) Module and the DCM chapter in Xilinx UG331: Spartan-3 Generation FPGA User Guide.

Interface Clock (IFCLK)

 The IFCLK line synchronizes the communication between the EZ-USB FX2LP USB FX2 microcontroller and the FPGA as detailed in the table below .

Scroll pdf title
titleInterface clock (IFCLK) signal details.

signal

FPGA pin

FPGA ball

FPGA bank

IFCLK

IO_L31N_1
TRDY1
RHCLK3

P25

1