...
Table 9: SPI bus modes for configuration.
The PROM file (containing the FPGA configuration bitstream) can be written to the SPI serial Flash memory (slave) also through the SPI pins of B2B connector JM5 (attached device set to master mode). In this case, the FPGA shall be turned off or three-stated to release its shared SPI pins and the USB FX2 microcontroller shall three-state (Z = high impedance) its shared SPI pins.
A plurality of usage combinations of the SPI bus during operation is made available to the user as suggested in Table 10.
description | usage | EZ-USB FX2LP | FPGA | B2B JM5 | serial Flash |
EZ-USB â—„â-º Flash | custom | master | off | deselected | slave |
FPGA â—„â-º Flash | custom | inactive | master | deselected | slave |
B2B JM5 â—„â-º Flash | custom | inactive | off | master | slave |
EZ-USB â—„â-º B2B JM5 | custom | master | off | slave | deselected |
EZ-USB â—„â-º B2B JM5 | custom | slave | off | master | deselected |
Table 10: SPI bus modes for operation.
Other combinations of master and slave units are neither supported nor recommended.