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All signals entering and exiting a Xilinx Spartan-3 generation FPGA must pass through the I/O resources, known as I/O blocks or IOBs. Users can specify the configuration for any unused IOB pins. This is the serial data outputs for all JTAG instruction and data registers.
This options are set graphically in Xilinx ISE Software Project Navigator by selecting the following:
Generate Programming File > Process Properties > Configuration Options > Unused IOB Pins
Select an option from the drop-down list.

1. Pull DownDefault. All unused I/O pins and input-only pins have a pull-down resistor to GND.
2. Pull UpAll unused I/O pins and input-only pins have a pull-up resistor to the VCCO_# supply for its associated I/O bank.
3. Float (also: Pullnone)All unused I/O pins and input-only pins are left floating (Hi-Z, high-impedance, three-state). Use external pull-up or pulldown resistors or logic to apply a valid signal level.