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Scroll pdf title
titlePin-out of B2B connector JM5
sup
ply		banktypeFPGA
pin		FPGA
ball		JM5
signal		JM5pinJM5
singal		FPGA
ball		FPGA
pin		typebanksup
ply
TE-in--Vb2b12Vb2b--in-TE
TE-in--Vb2b34Vb2b--in-TE
3.3V1I/O (I2C)IO_L13P_1Y22SCL56/MR--in-3.3V
3.3V1I/O (I2C)IO_L13N_1Y23SDA78/RESETA2PROG_Bin
CONFIG		2VccAux
3.3V
GNDGNDGND--GND910DONEAB21DONEout
CONFIG		VccAuxVccAux
3.3V2I/O
DUAL		IO_L22N_2
DOUT		AE15DOUT1112SPI_DAB15IO_L30N_2
MOSI/CSI_B		SPI in
DUAL		23.3V
3.3V2I/O
DUAL		IO_L01N_2
M0		AD4M01314INIT_BAA15IO_L34P_2
INIT_B		I/O
DUAL		23.3V
3.3V2I/O
DUAL		IO_L01P_2
M1		AC4M11516Vsup--out-TE
3.3V2I/O
DUAL		IO_L02P_2
M2		Y7M21718SPI_QAF24IO_L52P_2
D0/DIN/MISO		SPI out
DUAL		23.3V
3.3V2I/O
DUAL		IO_L07P_2
RDWR_B		Y12RDWR _B1920SPI_/SAA7IO_L02N_2
CSO_B		SPI out
DUAL		23.3V
VccAuxVccAuxin
CONFIG		PROG_BA2B2B _PROGB2122SPI_/CAE24IO_L52N_2
CCLK		SPI out
DUAL		23.3V
3.3 V-out--3.3V2324D4AE12IO_L24N_2
D4		I/O
DUAL		23.3V
3.3V2I/O
PWRMGMT		IO_L22P_2
AWAKE		AD15AWAKE2526D5AF12IO_L24P_2
D5		I/O
DUAL		23.3V
VccAuxVccAuxin
PWRMGMT		SUSPENDV20SUSPEND2728D6AF10IO_L22N_2
D6		I/O
DUAL		23.3V
3.3V2I/O
DUAL		IO_L36N_2
D1		AE18D12930GND--GNDGNDGND
3.3V2I/O
DUAL		IO_L36P_2
D2		AF18D23132D7AE10IO_L22P_2
D7		I/O
DUAL		23.3V
3.3V2I/O
DUAL		IO_L34N_2
D3		Y15D33334J5-IO20AA18IO_L47N_2I/O23.3V
3.3V2I/O
GCLK		IO_L27P_2
GCLK0		Y14J5-IO013536J5-IO21AB18IO_L47P_2I/O23.3V
GNDGNDGND--GND3738J5-IO22AE23IO_L48N_2I/O23.3V
3.3V2I/O
GCLK		IO_L28P_2
GCLK2		AF14J5-IO023940J5-IO23AF23IO_L48P_2I/O23.3V
3.3V2I/OIO_L29N_2AC14J5-IO034142J5-IO24AE25IO_L51P_2I/O23.3V
3.3V2I/OIO_L39N_2AE20J5-IO0443441.2V--out-1.2 V
3.3V2I/OIO_L39P_2AF20J5-IO054546J5-IO25AF25IO_L51P_2I/O23.3V
3.3V2I/OIO_L40N_2AC19J5-IO064748J5-IO26Y9IO_L05N_2I/O23.3V
3.3V2I/OIO_L40P_2AD19J5-IO074950J5-IO27W9IO_L05P_2I/O23.3V
GNDGNDGND--GND5152J5-IO28AF3IO_L06N_2I/O23.3V
3.3V2I/OIO_L41N_2AC20J5-IO085354J5-IO29AE3IO_L06P_2I/O23.3V
3.3V2I/OIO_L41P_2AD20J5-IO095556J5-IO30AF4IO_L07N_2I/O23.3V
3.3V2I/OIO_L42N_2U16J5-IO105758GND--GNDGNDGND
3.3V2I/OIO_L42P_2V16J5-IO115960J5-IO31AE4IO_L07P_2I/O23.3V
3.3V2I/OIO_L43N_2Y17J5-IO126162J5-IO32AD6IO_L08N_2I/O23.3V
3.3V2I/OIO_L43P_2AA17J5-IO136364J5-IO33AC6IO_L08P_2I/O23.3V
2.5 V-out--2.5V6566J5-IO34W10IO_L09N_2I/O23.3V
3.3V2I/OIO_L44N_2AD21J5-IO146768J5-IO35V10IO_L09P_2I/O23.3V
3.3V2I/OIO_L44P_2AE21J5-IO156970J5-IO36Y13IO_L25N_2
GCLK13		I/O
GCLK		23.3V
3.3V2I/OIO_L45N_2AC21J5-IO167172GND--GNDGNDGND
3.3V2I/OIO_L45P_2AD22J5-IO177374J5-IO37AA13IO_L25P_2
GCLK12		I/O
GCLK		23.3V
3.3V2I/OIO_L46N_2V17J5-IO187576J5-IO38AE13IO_L26N_2
GCLK15		I/O
GCLK		23.3V
3.3V2I/OIO_L46P_2W17J5-IO197778J5-IO39AF13IO_L26P_2
GCLK14		I/O
GCLK		23.3V
GNDGNDGND--GND7980J5-IO40W13IO_L20N_2I/O23.3V

 

 

 Signal Integrity Consideration  

 Traces of differential signals pairs are :

  • NOT routed symmetrically (as symmetric pairs).
  • NOT routed with equal length.
  • routed with a differential impedance between the two traces of 60 ohm.

For applications where traces length has to be matched or timing differences have to be compensated, Table 42 and Table 43 list the trace length of I/O signal lines measured from FPGA balls to B2B connector pins.

Pairs of pins that form a differential I/O pair appear colored together in the table. An electronic version of these pin-out tables are available for download from the Trenz Electronic support area of the web site.