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Scroll pdf title
titleDip switch S1B settings overview (power rails 1.2 V, 1.5V and 2.5 V only).

S1B position

Default position

Effect on 1.2 V, 1.5 V and 2.5 V rails

FX2 PON (off, open) 

(tick)

Power rails 1.2 V, 1.5 V and 2.5 V controlled by USB FX2 microcontroller (signal FX2_PS_EN)

PS_EN = FX2_PS_EN = 1 or 0

PON (on, closed)

(error)

Power rails 1.2 V, 1.5 V and 2.5 V always enabled (PS_EN = 1)

PS_EN ≠ FX_PS_EN = 1 or 0


Signal FX2_PS_EN

To command signal FX2_PS_EN, read the reference firmware code.
IOD = 0x03; // Enable PS_EN and disable PROG_B
OED = 0x03; // Configure PS_EN and PROG as outputs

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Scroll pdf title
titleTable from EZ-USB(R) Technical Reference Manual (EZ-USB_TRM.pdf).
Port D Pin
Alternate
Function
Alternate Function
is Selected By...
Alternate Function
is Described in...
PD[7:0]FD[15:8]

IFCFG1 = 1 and

any WORDWIIDE bit = 1
Slave FIFOs chapter 9 on page 99


Signal PS_EN

  • Signal PS_EN enables (1) or disables (0) power rails 1.2 V, 1.5 V and 2.5 V.

    Scroll pdf title
    titlePower rails 1.2 V, 1.5 V and 2.5 V could be enabled/disabled by signal PS_EN.


    Power-rail 3.3V is not controlled by signal PS_EN and is unconditionally enabled. 

    Scroll pdf title
    titlePower rails 3.3V could not be enabled/disabled by signal PS_EN.

     

VCCIO assembly options

 According to the corresponding assembly option, power rail VCCCIO0 can depend or not on the power rail 2.5V.

VCCIO0 voltage can be configured in 3 ways:

  • 2.5V - When resistor R103 is populated and resistor R102 is not populated.
  • 3.3V - When R103 is not populated and resistor R102 is populated.
  • 1.2 V ÷ 3.3 V (External supply) - When R103 is not populated and R102 is not populated. In this case external supply source have to be connected to pins 1, 2, 3, 4 of J4 B2B connector(1).

 (1) See Spartan-6 documentation fo VCCIO power range.

Scroll pdf title
titleExample of VCCIO0 assembly not dependent on 2.5V power rail. The other way is also possible.
Others options of VCCIO0 power supply are not supported and can damage the FPGA!

See the figure below to locate R102 and R103 on PCB.

Scroll pdf title
titleThis figure locates R102 and R103 on PCB.

Dip Switch S1B = FX2 PON 

When Dip switch S1B is in the left position ( = FX2 PON : power rails conditionally on depending on signal FX2_PS_EN), signal PS_EN is set to signal FX2_PS_EN (PS_EN = FX2_PS_EN) driven by the EZ-USB FX2LP USB FX2 microcontroller under user control (IOD and OED of fw.c).

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    • FPGA core logic (1.2 V)
    • DDR SDRAM (2.5 V)
    • FPGA bank 1 (1.5 V)
    • VREF1 (0.75 V)
    • VCCCIO0 (2.5 V) FPGA bank 0 (if R102+R103- assembly)

Dip Switch S1B = PON 

Full power operation (PS_EN = 1): when Dip switch S1B is in the right position (PON = power rails unconditionally on), signal PS_EN is set to power rail 3.3V. Thus power rails 1.2 V, 1.5 V and 2.5 V are unconditionally enabled.

Scroll pdf title
titleS1B on position PON (PS_EN ≠ FX2_PS_EN = x; PS_EN = high ).

 
 

 

Summary table

The table below summarizes all switching options implied by Dip switch S1B and firmware signal FX2_PS_EN (under the standard assembly option).

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