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A total of 110 FPGA user I/Os are available on corresponding contacts of B2B connectors J4 and J5 (see Appendix).

• 37 differential digital I/O pairs:each pair is configurable as 2 single-ended digital I/Os, corresponding to a maximum of 74 single-ended digital I/Os;
• 4 differential clock input pairs:each pair is configurable as differential digital I/O pair or 2 single-ended clock inputs or 2 single-ended digital I/Os (or combination thereof), corresponding to from a maximum of 8 independent clock inputs to a maximum of 8 independent digital I/Os;
• 1 differential clock input pair:the pair is configurable as differential digital input pair or as 2 single-ended clock inputs or 2 single-ended digital inputs (or combination thereof), corresponding to from a maximum of 2 independent clock inputs to a maximum of 2 independent digital inputs;
• 21 single-ended digital I/Os;
• 5 single-ended inputs.

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The micromodule has a total of 42 differential signal pairs routed pairwise with a differential impedance of 100 ohm to adjacent connector pins. These lines can be used for high speed signaling up to 666 Mbit/s per differential pair (see Xilinx Application Note XAPP485).