Page History
...
| Warning |
|---|
| If you don't also write the SPI Flash memory, the new bitstream image is lost if the TE USB FX2 module goes under reset or power off/on cycle. |
The Xilinx Spartan-3E FPGA on the TE0300, Xilinx Spartan-3A DSP FPGA on the TE0320, Xilinx Spartan-6 FPGA on the TE0630 can be configured in the following ways:
- B2B connector
- JTAG
- Slave Parallel (SelectMAP)
- Slave Parallel
- 6-pin JTAG header connector
- USB connector (in fact, SPI Flash memory is used)
SPI Flash memory (see the next section)
| Note |
|---|
| Programming using JTAG interface provide convenient and fast way to test FPGA project. FPGA configuration programmed this way is volatile and lost after reset or power cycle. |
For further information on
- Xilinx Spartan-3E FPGA
- Xilinx Spartan-3A DSP configuration modes, please consult the documentation listed in chapter 17 Related Materials and References.
- Xilinx Spartan-6
...
SPI Flash Configuration (bitstream, PROM image)
...
Overview
Content Tools