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The Spartan-3E architecture organizes I/Os into four I/O banks (see the table below).
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Voltage for banks B1, B2 and B3 is fixed respectively to 2,5 V, 3,3 V and 3,3 V.
Voltage VccIO for bank B0 shall span from 1.2 V to 3.3 V. VccIO can be supplied either externally or internally to the micromodule.
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| Spartan-3 I/Os are not 5 V tolerant. Applying more than the recommended operating voltages at any pin, results in a damaged FPGA (see Xilinx Answer AR#19146). |
VccIO can be externally supplied over the B2B connector J4. If bank B0 is not used, then VccIO can be left open.
If VccIO is not externally supplied, it can be internally supplied by one of the internal power rails of 2.5 V and 3.3 V. This is possible by short-circuiting one of the two pad pairs placed on the right of connector J4 at the top right corner of the bottom side of the micromodule.
Two suitable ways of shirt-circuiting the paid pair are by means of
- a zero-ohm 0603 (1608 metric) chip resistor or
- a solder blob.
This figure shows how to short-circuit VccIO to internal 3.3 V power rail.
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This figure shows how to short-circuit VccIO to internal 2.5 V power rail.
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