Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

  • Power supply.
  • Configuration by means of the Firmware Upgrade Tool (FUT), recommended for field upgrades. Please use a dedicated JTAG Adapter during development.
  • Data communication channel during operation.

...

 

Scroll pdf title
titleUSB pins at B2B connector J5.

pin number

pin name

signal name

description

7

B2B_D_P

D_P

USB data + (D+)

9

B2B_D_N

D_N

USB data - (D-)

TE0300 USB Controller

TE0300 is equipped with a Cypress EZ-USB FX2 controller to provide a high-speed USB 2.0 interface. The controller uses 4 interfaces (See chapter Block Diagram):

  • USB interface (to USB connector);
  • I2C interface (to EEPROM);
  • SPI interface (to FPGA and Flash);
  • FIFO interface (to FPGA).

The I2C interface connects the USB controller to the EEPROM chip, which stores vendor ID and device ID. See chapter DIP Switch for available options.
The SPI interface id used to communicate with the FPGA and to access the SPI serial Flash chip.
The FIFO interface provides a high-speed communication channel with the FPGA. The interface can transfer up to 48 MB/s burst rate.