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1. generate a bit-stream file from your Xilinx EDK design;

2. generate a fpga.bin PROM file from the bit-stream file (it is the same procedure of this the link before with only two difference: select BIN (swap bits ON) from the drop-down menu file format in the flash/PROM file property sub-panel and Any any other name than fpga for the output file name input field is not allowed)

3. generate a FWU file from the PROM file.

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