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FPGA project communicate with FX2 microcontroller using 8-bit synchronous Slave FIFO interface. All signals configured to active high level. When Host PC send data to COM port it comes to FX2 EP2 FIFO. FPGA project can read data from EP2, process it and write to EP6 FIFO. EP2 and EP6 FIFOs size is 512 bytes, quad buffered.
FPGA project should check FIFOs flags.

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title	Flags description

Signal	FX2 Flag	Description
FlagA	EP2EF	Receive FIFO empty flag. '1' When EP2 FIFO empty.
FlagB	EP6FF	Transmit FIFO full. '1' When EP6 FIFO full.
FlagC	EP6PF	Transmit FIFO almost full. '1' when less than 128 bytes free in EP6 FIFO.
FlagD	EP2PF	Receive FIFO almost full. '1' when more than 128 bytes in EP2 FIFO.

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Trenz Electronic Documentation

[TE USB Suite]

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