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For your convenience, a reference video is available on the TrenzElectronic's Channel at YouTube.
For further reference, please read Xilinx XAPP974: Indirect Programming of SPI Serial Flash PROMs with Spartan-3A FPGAs and this discussion (in particular for TE0630 Spartan 6 module) on the Xilinx forum.

Warning

Direct SPI configuration is supported only up to Xilinx iMPACT version 11.x. See Xilinx AR#36156.

DIP Switches configuration

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  1. disable the master reset S1D (do not care about all other switches at write time);
  2. connect the Xilinx platform cable to JTAG connector J2 as described in paragraph JTAG connector J2;
  3. generate or locate the FPGA bitstream file you want to store on the memory;
  4. prepare an SPI PROM file using the ISE iMPACT graphical software from the FPGA bitstream file;
  5. use the ISE iMPACT graphical software to in-system program the SPI PROM.

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Scroll pdf title
titleS1 settings for booting from SPI Flash memory.

switch

S1A
(EEPROM serial data)

S1B
(M2)

S1C
(M1)

S1D
(/MR master reset)

S2
(PS_EN)

state

0 = ON

0 = ON

0 = ON

1 = OFF

X = do note care

state

1 = OFF

0 = ON

0 = ON

1 = OFF

FX2 PON

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