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disable the master reset S1D (do not care about all other switches at write time);
connect the Xilinx platform cable to JTAG connector J2;
generate or locate the FPGA bitstream file you want to store on the memory;
prepare an SPI PROM file using the ISE iMPACT graphical software from the FPGA bitstream file (link);
use the ISE iMPACT graphical software to in-system program the SPI PROM (link).

In order to have the module to configure from its SPI Flash memory next time it is (re)booted, ensure one of following DIP switch settings:

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