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The Logic Architecture Layer (FPGA image contained in a FPGA bitstream) actually changes (the SPI Flash content (FPGA bitstream) programs/configures the FPGA) only when .

  • the user resets the TE USB FX2 module (Powered reset);
  • the user power off and power on the TE USB FX2 module (Power-on reset);
  • the user use the USB FX2 API Command (FW API)'s POWER to realize a power cycle (off/on) that affect the FPGA only (not the entire TE-USB module).
Note
The user could also directly write the FPGA bitstream (.bit file) on the FPGA but, if the user does not also write the SPI Flash memory, the new bitstream image is lost if the TE USB FX2 module undergoes a reset or a power off/on cycle.