Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

  • Intel® MAX 10 Commercial [10M08SAU169C8G]

    • Package: UBGA-169

    • Speed Grade: C8 (Slowest)

    • Temperature: 0°C to 85°C

    • Package compatible device 10M0210M08...10M16 as assembly variant on request possible

  • SDRAM Memory up to 64Mb, 166MHzDual High Speed USB to 32 Mbyte (8Mbyte default)

  • USB 2.0 Multipurpose UART/FIFO IC

  • 64 Mb Quad SPI Flash

  • 4Kb EEPROM Memory

  • 8x User LED 

  • (FT2232H)

    • 4 Kbit EEPROM Memory for FTDI configuration data
    • Micro USB Receptacle (communication and power)
  • SPI Flash - NOT INSTALLED (only special option)

  • 8x User LED Micro USB2 Receptacle 90
  • 18 Bit 2MSPS Analog to Digital Converter
  • 2x SMA Female Connector

  • I/O interface: 23x GPIO - Arduino MKR compatible

  • Power Supply: 5V

  • Dimension: 86.5mm x 25mm

  • Others:

    • Instrumentation Amplifier

    • Differential Amplifier

    • Operational Amplifier

...

  1. SMA Connector, J5...6

  2. Amplifier, U12 - U14 - U6

  3. Series Voltage Reference, U8

  4. Analog to Digital Converter, U15

  5. Voltage Regulator, U10 - U13 - U16

  6. Switching Voltage Regulator/LDO, U11 - U4

  7. SDRAM Memory, U2

  8. Intel® MAX 10 FPGA, U1
  9. SPI Flash Memory, U5

  10. 12.00 MHz MEMS oscillator, U7

  11. FTDI USB2 to JTAG/UART adapter, U3

  12. User LEDs, D2...9

  13. FTDI configuration EEPROM, U9

  14. Configuration/Status LED (Red) , D10

  15. Power-on LED (Green), D1

  16. Push button, S1...2

  17. Micro USB Connector, J9

  18. 1x14 pin header, J2 (Not assembled)

  19. 1x6 pin header, J4 (Not assembled)

  20. 1x4 Header, J3 (Not assembled)

  21. 1x14 pin header, J1 (Not assembled)

...

Scroll Title
anchorTable_OV_IDS
titleInitial delivery state of programmable devices on the module

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SDRAM

Storage device name

Content

Notes

Quad SPI Flash

N/A

Not

Programmed

populated

EEPROM

Programmed

FTDI configuration

Not Programmed


Configuration Signals

Page properties
hiddentrue
idComments
  • Overview of Boot Mode, Reset, Enables.

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface

...

(using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.

...

To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.

...

FPGA Reconfigration can be triggered by pressing push button S1.

Scroll Title
anchorTable_OV_RST
titleReset process.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signal

Push ButtonPin HeaderNote

RESET

S1J2Connected to nCONFIG


...

Scroll Title
anchorTable_OBP_IOs
titleFPGA I/O Banks


FPGA BankI/O Signal CountConnected toNotes
Bank 1A71x14 Pin header, J1AIN0...6
1Jumper, J3AIN7
Bank 1B51x6 Pin header, J4JTAG_EN, TDI, TDO, TMS, TCK
Bank 2


41x14 Pin header, J1D2...5
5A2D, U15ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV
112MHz Oscillator, U7CLK12M
2Amplifier, U12nIAMP_A0, nIAMP_A1
Bank 322SDRAM, U2RAM_ADDR_CMD
Bank 59

1x14 Pin header, J2

DIO6...14
21x14 Pin header, J1DIO0...1
1D12_RDIO12
Bank 616SDRAM, U2DQ0...15
2SDRAM, U2DQM0...1
1D11_RDIO11
Bank 8



8User Red LEDs, D2...9LED0...7
6SPI Flash, U5F_CS, F_CKL, F_DI, F_DO, nSTATUS, DEVCLRn
1Red LED, D10CONF_DONE
6FTDI JTAG/UART Adapter, U3BDBUS0...5
1Push Button, S2USER_BTN


Micro-

...

USB Connector

The Micro-USB2 USB connector J9 provides an interface to access the FIFO/UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that FTDI USB driver is drivers are installed on your host PC.

...

JTAG access to the TEI0015 SoM through pin header connector J4. This is normally not needed as there is on-board USB JTAG functionality.

Scroll Title
anchorTable_SIP_JTG
titleJTAG pins connection

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

JTAG Signal

Pin Header Connector

Note
TMSJ4-6
TDIJ4-5
TDOJ4-4
TCK

J4-3


JTAG_ENJ4-2Pulled-up to 3.3V


...

Scroll Title
anchorTable_OBP
titleOn board peripherals

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Chip/InterfaceDesignatorNotes
77530153U2
FTDI FT2232HU3JTAG/UART Adapter/FIFO
SPI FlashU5
77530153U9
OscillatorU712 MHz clock source
77530153U12, U14Analog to Digital Converter
Push ButtonsS1...2
8x User LEDsD2...9Red LEDs


...

Scroll Title
anchorTable_OBP_SDRAM
titleSDRAM interface IOs and pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SDRAM I/O Signals

Signal Schematic Name

Connected toNotes
Address inputs

A0 ... A13

bank 3-
Bank address inputs

BA0 / BA1

bank 3

-
Data input/output

DQ0 ... DQ15

bank 6

-
Data mask

DQM0 ... DQM1

bank 6

-
ClockCLKbank 3-
Control Signals

CS

bank 3

Chip select

CKE

bank 3

Clock enable

RAS

bank 3

Row Address Strobe

CAS

bank 3

Column Address Strobe

WEbank 3Write Enable


FTDI FT2232H

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG, 6 I/O's of . Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfacesis configured to be used as in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.

The configuration of FTDI FT2232H chip is pre-programmed on in the EEPROM U9.

Scroll Title
anchorTable_OBP_FTDI
titleFTDI chip interfaces and pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

FTDI Chip U3 PinSignal Schematic NameConnected toNotes
ADBUS0TCKFPGA bank 1B, pin G2JTAG interface
ADBUS1TDIFPGA bank 1B, pin F5
ADBUS2TDOFPGA bank 1B, pin F6
ADBUS3TMS

FPGA bank 1B, pin G1

BDBUS0BDBUS0FPGA bank 8, pin A4User configurable
BDBUS1BDBUS1FPGA bank 8, pin B4User configurable
BDBUS2BDBUS2FPGA bank 8, pin B5User configurable
BDBUS3BDBUS3FPGA bank 8, pin A6User configurable
BDBUS4BDBUS4FPGA bank 8, pin B6User configurable
BDBUS5BDBUS5FPGA bank 8, pin A7User configurable

SPI Flash

BDBUS6BDBUS6FPGA bank 6, pin C11
BDBUS7BDBUS7FPGA bank 3, pin J7
BCBUS0BCBUS0FPGA bank 5, pin J9
BCBUS1BCBUS1FPGA bank 3, pin K5
BCBUS2BCBUS2FPGA bank 3, pin L4
BCBUS3BCBUS3FPGA bank 3, pin L5
BCBUS4BCBUS4FPGA bank 3, pin N12


SPI Flash

Optional SPI flash device maybe assembled in custom variants, normally it is not populatedOn-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.

Scroll Title
anchorTable_OBP_QSPI
titleQuad SPI Flash memory interface

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signal Schematic NameConnected toNotes
F_CSFPGA bank 8, pin B3Chip select
F_CLKFPGA bank 8, pin A3Clock
F_DIFPGA bank 8, pin A2Data in / out
nSTATUS

FPGA bank 8, pin C4

Data in / out, configuration dual-purpose pin of FPGA
DEVCLRNFPGA bank 8, pin B9Data in / out, configuration dual-purpose pin of FPGA
F_DOFPGA bank 8, pin B2Data in / out


...

The configuration of FTDI FT2232H chip is pre-programmed on in the EEPROM U9.

Scroll Title
anchorTable_OBP_EEP
titleI2C EEPROM interface MIOs and pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SchematicConnected toNotes

EECS

FTDI U3, Pin EECS
EECLKFTDI U3, Pin EECLK
EEDATAFTDI U3, Pin EEDATA


...

Scroll Title
anchorTable_OBP_CLK
titleOsillators

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Clock SourceSchematic NameFrequencyNote
Microchip MEMS Oscillator, U7CLK12M12.00 MHz

Connected to FTDI FT2232 U3, pin 3.

Connected to FPGA SoC bank 2, pin H6.


...

Page properties
hiddentrue
idComments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

To power-up the module, power supply with minimum current capability of 1A is recommendedThe module is power supplied from USB (optionally via unpopulated pin header).

Power Consumption

Scroll Title
anchorTable_PWR_PC
titlePower Consumption

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

FPGATypical Current
Intel MAX 10 10M08 FPGA SoCFPGATBD*


* TBD - To Be Determined

...

Scroll Title
anchorTable_RH_DCH
titleDocument change history.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateRevisionContributorDescription

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse

Page info
infoTypeModified by
typeFlat
showVersionsfalse

  • multiple sections updated

2020-02-04

Feb 2020

v.98ED
  • Technical Specifications updated

  • Power Rails updated

--

all

Page info
infoTypeModified users
typeFlat
showVersionsfalse

  • --


...