Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Page properties
hiddentrue
idComments

Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.


Scroll pdf ignore

Table of Contents

Table of Contents

...

The Trenz Electronic TE0716 is a commercial-grade* SoM (System on Module) based on Xilinx Zynq-7000 SoC XC7Z020*, with 1GB of DDR3L-1600 SDRAM*, 32MB of SPI flash memory, 10x 12-Bit Low Power SAR ADCs, 512Kb Serial EEPROM, Gigabit Ethernet PHY transceiver, a an USB PHY transceiver, a single chip USB 2.0 to UART/JTAG Interface (Xilinx License included), and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os are provided via rugged high-speed board-to-board connectors.

Refer to http://trenz.org/te0716-info for the current online version of this manual and other available documentation.

Notes: * standard values but depends on assembly version. Additional assembly options are available for cost or performance optimization upon request.

Page properties
hiddentrue
idComments

Notes :

...

Page properties
hiddentrue
idComments

Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modules and mainboards:

  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2...ZU5*
    • Engine: CG, EG, EV*
    • Speed: -1LI, -2LE,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS
      • Data width: 32bit
      • Size: def. 2GB*
      • Speed:***
    • eMMC
      • Data width: 8Bit
      • size: def. 8GB *
    • QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 128MB *
    • HyperRAM/Flash (optional, default not assembled)
      • size:*
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Lattice LCMXO2
    • PLL SI5338
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  • Interface
    • 132 x HP PL I/Os (3 banks)
    • ETH
    • USB
    • 4 GTR (for USB3, Sata, PCIe, DP)
    • MIO for UART
    • MIO for SD
    • MIO for PJTAG
    • JTAG
    • Ctrl
  • Power
    • 3.3V-5V Main Input
    • 3.3V Controller Input
    • Variable Bank IO Power Input
  • Dimension
    • 4 cm x 5 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension


  • SoC/FPGA
    • Package: SFVC784 CLG484
    • Device: Xilinx Z-7020
    • Speed: -1 *
    • Temperature: C grade *.
  • Xilinx XC7Z020 SoC:
    • Processing system (PS):
      • ARM® CortexTM-A9 MPCoreTM with CoreSightTM.
      • L1 Cache: 32KB Instruction, 32KB Data per processor.
      • L2 Cache: 512KB.
    • Programmable logic (PL):
      • Artix-7 FPGA Equivalent.
      • Logic cells: 85K.
      • Look-Up Tables: 53200.
      • Block RAM: 4.9 Mb.
      • DSP slices: 220.
      • Peak DSP performance: 276 GMACs.
      • 2x 12 bit, 1 MSPS ADCs with up to 17 Differential Inputs.
    • 120 x PL HR I/O (48 differential pairs and 24 single-ended).
    • 2x PS MIOs (shared with UART TX/RX ZYNQ-FTDI).
  • 1GByte DDR3L SDRAM memory (2 x [256Mbit x 16]), 32-bit wide data bus.
  • 32MByte Quad SPI Flash memory.
  • MAC address serial EEPROM with EUI-48TM node identity (24AA025E48).
  • 512Kb Serial EEPROM memory (CAT24C512).
  • 10x 12-Bit Low Power SAR ADCs up to 2 MSPS (NCD98011).
  • Gigabit Ethernet transceiver PHY (Marvell 88E1512).
  • Highly integrated full-featured hi-speed USB 2.0 ULPI transceiver (Microchip USB3320C-EZK).
  • RAM/Storage
    • Low Power DDR3 SDRAM on PS
      • Data width: 32bit
      • Size: def. 1GB *
      • Speed: 1600 Mbps **
    • QSPI boot Flash
      • Data width: 4bit
      • size: 32MB *
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48).
    • 512Kb user MAC address serial EEPROM.
  • On Board
    • 10x 12-Bit Low Power SAR ADCs up to 2 MSPS (NCD98011).
    • Low Power Oscillators.
    • Gigabit Ethernet PHY transceiver (Marvell Alaska 88E1512).
    • High-Speed USB 2.0 ULPI transceiver with full OTG support (Microchip USB3320C).
    • Single chip High-Speed USB 2.0 to UART/JTAG Interface (Xilinx License included) (FTDI FT2232H).
    • 2x User RGB LEDs (Green), LED FPGA "Done" (Green).
    • 2x Tactile Switches (User), 1 x Tactile Switche (Reset).
  • Interface
    • 120x HR PL I/Os (3 banks).
    • 2x PS MIOs (shared with UART TX/RX ZYNQ-FTDI).
    • 1 Gbps RGMII Ethernet interface.
    • High Speed USB 2.0 ULPI with full OTG support.
    • High Speed USB 2.0 to UART/JTAG interface
    Single chip USB Interface 2.0 High Speed 480Mbs to UART / JTAG(Xilinx License included) (FTDI FT2232H-56Q)
    • , including microUSB-B connector.
  • 2xUser RGB LEDs (Green), LED FPGA DONE (Green).
  • 2 x Tactile Switches (User), 1 x Tactile Switche (Reset).
    • microSD™
    • JTAG
  • PowerCard Connector microSD™.
    • On-board high-efficiency DC-DC converters for all voltages used.
  • Dimension
      Board Size:
      • 65 x 45 mm
      .

    Block Diagram

    • Notes
      • * depends on assembly version
      • ** depends on used Zynq and DDR3 combination

    Block Diagram

    Page properties
    Page properties
    hiddentrue
    idComments

    add drawIO object here.

    Note

    For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


    ...

    Scroll Title
    anchorFigure_OV_BD
    titleTExxxx TE0716-01 block diagram


    Scroll Ignore

    draw.io Diagram
    borderfalse
    diagramNameDB-TE0716-01
    simpleViewerfalse
    width
    linksauto
    tbstylehidden
    diagramDisplayName
    lboxtrue
    diagramWidth641
    revision919


    Scroll Only

    Image RemovedImage Added



    Main Components

    ...

    Scroll Title
    anchorFigure_OV_MC
    titleTExxxx TE0716-01 main components


    Scroll Ignore

    draw.io Diagram
    borderfalse
    diagramNameMC-TE0716-01
    simpleViewerfalse
    width
    linksauto
    tbstylehidden
    diagramDisplayName
    lboxtrue
    diagramWidth641
    revision918



    Scroll Only

    Image Modified



    1. Xilinx Zynq XC7Z SoC, U5 (Top)
    2. 4Gbit DDR3/L SDRAM, U13 (Top)
    3. 4Gbit DDR3/L SDRAM, U12 (Top)
    4. 32MByte Quad SPI Flash memory, U7 (Top)
    5. 2Kbit MAC address serial EEPROM with EUI-48TM node identity, U24

    Initial Delivery State

    Page properties
    hiddentrue
    idComments

    Notes :

    Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

    If there is no components which might have initial data ( possible on carrier) you must keep the table empty

    ...

    anchorTable_OV_IDS
    titleInitial delivery state of programmable devices on the module

    ...

    Storage device name

    ...

    Content

    ...

    Notes

    ...

    Quad SPI Flash

    ...

    -

    ...

    -

    ...

    1. (Top)
    2. 512Kb Serial EEPROM memory, U21 (Top)
    3. 10x 12-Bit Low Power SAR ADCs, U1..U4, U10, U11, U15..U17, U19 (Top)
    4. High-speed USB 2.0 ULPI transceiver, U18 (Top)
    5. Single chip USB Interface 2.0 to UART / JTAG, U39 (Top)
    6. MicroUSB-B connector, J13 (Top)
    7. Low-power oscillator @ 12.000000MHz (OSCI-FTDI), U41 (Top)
    8. Low-power oscillator @ 25.000000MHz (ETH-CLK), U9 (Top)
    9. LED FPGA "Done" (Green) D3 (Top)
    10. User RGB LED 1 D4 (Top)
    11. User RGB LED 2 D5 (Top)
    12. Tactile Switch (User), S1 (Top)
    13. Tactile Switch (User), S2 (Top)
    14. Tactile Switch (Reset), S3 (Top)
    15. 5A Synchronous Buck DC-DC Converter (1V), U37 (Top)
    16. 2A Synchronous Buck DC-DC Converter (3.3V), U46 (Top)
    17. 2A Synchronous Buck DC-DC Converter (1.8V), U45 (Top)
    18. 2A Synchronous Buck DC-DC Converter (1.5V), U43 (Top)
    19. 250mA Ultra-Low Noise LDO Regulator (3.3V_ADC Digital I/O supply), U23 (Top)
    20. 250mA Ultra-Low Noise LDO Regulator (ADC_VAA Analog supply/reference, 3.3V), U38 (Top)
    21. Gigabit Ethernet PHY transceiver, U8 (Bottom)
    22. Low-power oscillator @ 33.333333MHz (PS-CLK), U6 (Bottom)
    23. 3A Sink/Source DDR Termination Regulator (VTT/VTTREF, 0.75V), U47 (Bottom)
    24. Card Connector microSD™, J2 (Bottom)
    25. 2x60 positions high speed/density plug connector, JP1 (Bottom)
    26. 2x60 positions high speed/density plug connector, JP2 (Bottom)


    Initial Delivery State

    Page properties
    hiddentrue
    idComments

    Notes :

    Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

    If there is no components which might have initial data ( possible on carrier) you must keep the table empty


    Scroll Title
    anchorTable_OV_IDS
    titleInitial delivery state of programmable devices on the module

    Scroll Table Layout
    orientation

    Configuration Signals

    Page properties
    hiddentrue
    idComments
    • Overview of Boot Mode, Reset, Enables.

    Boot process.

    The TE0716 supports QSPI and SD Card boot modes, which is controlled by the insertion of the SD card before powering on.

    Boot Mode
    Scroll Title
    anchorTable_OV_BP
    titleBoot process.

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Storage device name

    IC Designator

    Content

    SD Card State

    Notes

    SD card inserted

    SD Card (J2)

    -SD card not presentQSPI (U7)-

Reset process.

The nRST signal active low reset input, forces PS_POR_B to apply a master reset of the entire Zynq. This reset could be manually done by pressing a switch. This signal could be also reached by a B2B large connector.

This nRST signal (active low) is also held until all FPGA power supplies set their Power Good signals.

Furthermore, if the FPGA core voltage drops under 0.84V or the 3.3V power supply drops to 2.94V or less, this nRST signal is also activated by the Voltage Monitor.

See more about the Power-on Reset (PS_POR_B) signal in the “Zynq-7000 SoC Technical Reference Manual” (“UG585”).

Quad SPI Flash

U7Empty

-

512Kb Serial EEPROMU21Empty

-

2Kb 24AA025E48 EEPROMU24Pre-programmed globally unique, 48-bit node address (MAC).-
4Kb M93C66-R EEPROMU40Xilinx JTAG Programmer LicenseFor FTDI IC only (U39).



Configuration Signals

Page properties
hiddentrue
idComments
  • Overview of Boot Mode, Reset, Enables.

Boot process.

The TE0716 supports QSPI and SD Card boot modes, which is controlled by the insertion of the SD card before powering on.

Scroll Title
anchorTable_OV_BP
titleBoot process.

Scroll Table Layout
orientationportrait
sortDirectionASC

Scroll Title
anchorTable_OV_RST
titleReset process.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signal

B2BI/ONote

nRST

JP2-4--
nRST-S3-

Signals, Interfaces and Pins

Page properties
hiddentrue
idComments

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

SD Card State

Boot ModeNotes

SD card inserted

SD Card (J2)

-
SD card not presentQSPI (U7)-



Reset process.

The nRST signal active low reset input, forces PS_POR_B to apply a master reset of the entire Zynq. This reset could be manually done by pressing a switch. This signal could be also reached by a B2B large connector.

This nRST signal (active low) is also held until all FPGA power supplies set their Power Good signals.

Furthermore, if the FPGA core voltage drops under 0.84V or the 3.3V power supply drops to 2.94V or less, this nRST signal is also activated by the Voltage Monitor.

See more about the Power-on Reset (PS_POR_B) signal in the “Zynq-7000 SoC Technical Reference Manual” (“UG585”).Zynq SoC's I/O banks signals connected to the B2B connectors:

3.3V
Scroll Title
anchorTable_SIPOV_B2BRST
titleGeneral PL I/O to B2B connectors informationReset process.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

FPGA Bank

Signal

B2B
Connector
I/O
Signal Count
Voltage Level
Note
NotesMIO 500JP12

nRST

JP2-4--
nRST-
HR 35
S3
JP1483.3V-HR 13JP2503.3V-HR 33JP2223.3V-

...

-


Signals, Interfaces and Pins

Page properties
hiddentrue
idComments

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B)

FPGA IOs

Zynq SoC's I/O banks signals connected to the B2B connectors:JTAG access to the TExxxx SoM through B2B connector JMX.

Scroll Title
anchorTable_SIP_JTGB2B
titleJTAG pins connectionGeneral PS-PL I/O to B2B connectors information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

JTAG Signal
FPGA BankB2B Connector
TMSJP2-7
TDIJP2-11
TDOJP2-10
TCK

JP2-8

MIO Pins

I/O Signal CountVoltage LevelNotes
MIO 500JP123.3V-
HR 35JP1483.3V-
HR 13JP2503.3V-
HR 33JP2223.3V-



JTAG Interface

JTAG access to the TE0716 SoM through B2B connector JP2. The TE0716 is also provided with a FTDI USB-to-JTAG adapter connected to the MicroUSB connector J13, but ONLY ONE connection for JTAG should be used at the time!.

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

B2B
scroll
Page properties
hiddentrue
idComments
MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI
scroll-title
anchorTable_SIP_MIOsJTG
titleMIOs JTAG pins connection

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

JTAG Signal

B2B Connector

MIO PinConnected to

Notes
15UART_TX_ZYNQJP1-70Also Connected to U36-2. To use this signal from B2B connector, "UART_OB_DISABLE" (JP1-11) must be "High".14UART_RX_ZYNQJP1-71Also Connected to U36-3. To use this signal from B2B connector, "UART_OB_DISABLE" (JP1-11) must be "High".