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Table of Contents

Table of Contents

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The Trenz Electronic TE0716 is a commercial-grade* SoM (System on Module) based on Xilinx Zynq-7000 SoC XC7Z020*, with 1GB of DDR3L-1600 SDRAM*, 32MB of SPI flash memory, 10x 12-Bit Low Power SAR ADCs, 512Kb Serial EEPROM, Gigabit Ethernet PHY transceiver, an USB PHY transceiver, a single chip USB 2.0 to UART/JTAG Interface (Xilinx License included), and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os are provided via rugged high-speed board-to-board connectors.

Refer to http://trenz.org/te0716-info for the current online version of this manual and other available documentation.

Notes: * standard values but depends on assembly version. Additional assembly options are available for cost or performance optimization upon request.

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Notes :

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  • SoC/FPGA
    • Package: CLG484
    • Device: Xilinx Z-7020
    • Speed: -1 *
    • Temperature: C grade *.
  • RAM/Storage
    • Low Power DDR3 SDRAM on PS
      • Data width: 32bit
      • Size: def. 1GB *
      • Speed: 1600 Mbps **
    • QSPI boot Flash
      • Data width: 4bit
      • size: 32MB *
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48).
    • 512Kb user MAC address serial EEPROM.
  • On Board
    • 10x 12-Bit Low Power SAR ADCs up to 2 MSPS (NCD98011).
    • Low Power Oscillators.
    • Gigabit Ethernet PHY transceiver (Marvell Alaska 88E1512).
    • Hi-speed USB2 High-Speed USB 2.0 ULPI transceiver with full OTG support (Microchip USB3320C).
    • Single chip High-Speed USB 2.0 to UART/JTAG Interface (Xilinx License included) (FTDI FT2232H).
    • 2xUser RGB 2x User RGB LEDs (Green), LED FPGA DONE "Done" (Green).
    • 2 x Tactile 2x Tactile Switches (User), 1 x Tactile Switche (Reset).
  • Interface
    • 120 x 120x HR PL I/Os (3 banks).
    • 2x PS MIOs (shared with UART TX/RX ZYNQ-FTDI).
    • 1 Gbps RGMII Ethernet interface.
    • High Speed USB2 Speed USB 2.0 ULPI with full OTG support.
    • High Speed USB 2.0 to UART/JTAG Interfaceinterface, including microUSB-B connector.
    • microSD™
    • JTAG

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Main Components

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  1. Xilinx Zynq XC7Z SoC, U5 (Top)
  2. 4Gbit DDR3/L SDRAM, U13 (Top)
  3. 4Gbit DDR3/L SDRAM, U12 (Top)
  4. 32MByte Quad SPI Flash memory, U7 (Top)
  5. 2Kbit MAC address serial EEPROM with EUI-48TM node identity, U24 (Top)
  6. 512Kb Serial EEPROM memory, U21 (Top)
  7. 10x 12-Bit Low Power SAR ADCs, U1..U4, U10, U11, U15..U17, U19 (Top)
  8. High-speed USB 2.0 ULPI transceiver, U18 (Top)
  9. Single chip USB Interface 2.0 to UART / JTAG, U39 (Top)
  10. MicroUSB-B connector, J13 (Top)
  11. Low-power oscillator @ 12.000000MHz (OSCI-FTDI), U41 (Top)
  12. Low-power oscillator @ 25.000000MHz (ETH-CLK), U9 (Top)
  13. LED FPGA DONE "Done" (Green) 13 d3 D3 (Top)
  14. User RGB LED 1 D4 (Top)
  15. User RGB LED 2 D5 (Top)
  16. Tactile Switch (User), S1 (Top)
  17. Tactile Switch (User), S2 (Top)
  18. Tactile Switch (Reset), S3 (Top)
  19. 5A Synchronous Buck DC-DC Converter (1V), U37 (Top)
  20. 2A Synchronous Buck DC-DC Converter (3.3V), U46 (Top)
  21. 2A Synchronous Buck DC-DC Converter (1.8V), U45 (Top)
  22. 2A Synchronous Buck DC-DC Converter (1.5V), U43 (Top)
  23. 250mA Ultra-Low Noise LDO Regulator (3.3V_ADC Digital I/O supply), U23 (Top)
  24. 250mA Ultra-Low Noise LDO Regulator (ADC_VAA Analog supply/reference, 3.3V), U38 (Top)
  25. Gigabit Ethernet PHY transceiver, U8 (Bottom)
  26. Low-power oscillator @ 33.333333MHz (PS-CLK), U6 (Bottom)
  27. 3A Sink/Source DDR Termination Regulator (VTT/VTTREF, 0.75V), U47 (Bottom)
  28. Card Connector microSD™, J2 (Bottom)
  29. 2x60 positions high speed/density plug connector, JP1 (Bottom)
  30. 2x60 positions high speed/density plug connector, JP2 (Bottom)

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Storage device name

IC Designator

Content

Notes

Quad SPI Flash

U7Empty

-

512Kb Serial EEPROMU21Empty

-

2Kb 24AA025E48 EEPROMU24Pre-programmed globally unique, 48-bit node address (MAC).-
4Kb M93C66-R EEPROMU40Xilinx JTAG Programmer License-For FTDI IC only (U39).



Configuration Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B)

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FPGA IOs

Zynq SoC's I/O banks signals connected to the B2B connectors:

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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
MIO 500JP123.3V-
HR 35JP1483.3V-
HR 13JP2503.3V-
HR 33JP2223.3V-



JTAG Interface

JTAG access to the TE0716 SoM through B2B connector JP2. The TE0716 is also provided with a FTDI USB-to-JTAG adapter connected to the MicroUSB connector J13, but ONLY ONE connection for JTAG should be used at the time!.

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JTAG Signal

B2B Connector

Notes
TMSJP2-73.3V Voltage level. Also Connected to U39 (FTDI)
TDIJP2-113.3V Voltage level. Also Connected to U39 (FTDI)
TDOJP2-103.3V Voltage level. Also Connected to U39 (FTDI)
TCK

JP2-8

3.3V Voltage level. Also Connected to U39 (FTDI)

VREF_JTAGJP2-5Module Vout

MIO Pins


UART Interface

The TE0716 provides UART access to the TE0716 SoM through B2B connector JP1. The TE0716 is also equipped with a FTDI USB-to-UART adapter connected to the MicroUSB connector J13, but ONLY ONE connection for UART should be used at the time! (please read "Notes" in the following table). The UART interface is connected to the Zynq UART PS (UART 0).

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

Connected to
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MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI
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MIO Pin

UART Signal

B2B Connector

Notes
15
UART_TX_ZYNQJP1-703.3V Voltage level. Also Connected to FTDI through U36
-2
. To use this signal from B2B connector, "UART_OB_DISABLE" (JP1-11) must be "High".
14
UART_RX_ZYNQJP1-713.3V Voltage level. Also Connected to FTDI through U36
-3
. To use this signal from B2B connector, "UART_OB_DISABLE" (JP1-11) must be "High".

Test Points

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Example:


USB Interface

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The TE0716 provides USB access to the TE0716 SoM through B2B connector JP2. The USB interface is connected later to the Zynq UART PS (USB 0), by using a USB PHY.


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Test Point

USB Signal

Connected to

B2B Connector

Notes
TP1+1.0V

U37, DC-DC Converter

PL-VCCINTTP2ADC_VAAU38, LDO Regulator
ADC_VAA Analog supply/reference, (3.3V)TP3+1.5VU43, DC-DC Converter-TP4+1.8VU45, DC-DC Converter-TP5VTTU47, DDR Termination Regulator(0.75V)TP6VTTREFU47, DDR Termination Regulator(0.75V)TP7+5.0VJP1-(1,2,3)
JP2-(1,2,3)Main Digital Power InputTP8+3.3VU46, DC-DC Converter-TP9+5.0V_VAAJP1-(43,44)Main Analog Low Power InputTP10+3.3V_ADCU23, LDO RegulatorADC's Digital I/O supplyTP11GND--TP12GND--TP13SPI-DQ3/M0MIO_5Remove SD card and short with TP14 for JTAG only modeTP14GND--

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

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Notes :

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USB_OTG_D_ PJP2-643.3V Voltage level.
USB_OTG_D_ NJP2-653.3V Voltage level.
USB_OTG_IDJP2-663.3V Voltage level.
USB_VBUS_E NJP2-673.3V Voltage level.
USB_VBUSJP2-68

Max. voltage: 5.5V


ETH Interface

The TE0716 provides ETH access to the TE0716 SoM through B2B connector JP1. The ETH interface is connected later to the Zynq Ethernet PS (Ethernet 0), by using a ETH PHY.

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ETH Signal

B2B Connector

Notes

PHY_MDI0_P

PHY_MDI0_ N

JP1-5

JP1-4

3.3V Voltage level.

PHY_MDI1_P

PHY_MDI1_ N

JP1-7

JP1-8

3.3V Voltage level.

PHY_MDI2_P

PHY_MDI2_ N

JP1-68

JP1-67

3.3V Voltage level.

PHY_MDI3_P

PHY_MDI3_ N

JP1-65

JP1-64

3.3V Voltage level.


ADC Interface

The analog inputs of the ADCs are connected to B2B connector JP1.

Designator
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ADC Signal

B2B Connector

Chip/Interface

Notes
Quad SPI FlashU7-