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Table of Contents
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The Trenz Electronic TE0716 is a commercial-grade* SoM (System on Module) based on Xilinx Zynq-7000 SoC XC7Z020*, with 1GB of DDR3L-1600 SDRAM*, 32MB of SPI flash memory, 10x 12-Bit Low Power SAR ADCs, 512Kb Serial EEPROM, Gigabit Ethernet PHY transceiver, an USB PHY transceiver, a single chip USB 2.0 to UART/JTAG Interface (Xilinx License included), and powerful switching-mode power supplies for all on-board voltages. A large number of configurable I/Os are provided via rugged high-speed board-to-board connectors.
Refer to http://trenz.org/te0716-info for the current online version of this manual and other available documentation.
Notes: * standard values but depends on assembly version. Additional assembly options are available for cost or performance optimization upon request.
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- SoC/FPGA
- Package: CLG484
- Device: Xilinx Z-7020
- Speed: -1 *
- Temperature: C grade *.
- RAM/Storage
- Low Power DDR3 SDRAM on PS
- Data width: 32bit
- Size: def. 1GB *
- Speed: 1600 Mbps **
- QSPI boot Flash
- Data width: 4bit
- size: 32MB *
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48).
- 512Kb user MAC address serial EEPROM.
- Low Power DDR3 SDRAM on PS
- On Board
- 10x 12-Bit Low Power SAR ADCs up to 2 MSPS (NCD98011).
- Low Power Oscillators.
- Gigabit Ethernet PHY transceiver (Marvell Alaska 88E1512).
- High-Speed USB 2.0 ULPI transceiver with full OTG support (Microchip USB3320C).
- Single chip High-Speed USB 2.0 to UART/JTAG Interface (Xilinx License included) (FTDI FT2232H).
- 2xUser RGB 2x User RGB LEDs (Green), LED FPGA "Done" (Green).
- 2 x Tactile 2x Tactile Switches (User), 1 x Tactile Switche (Reset).
- Interface
- 120 x 120x HR PL I/Os (3 banks).
- 2x PS MIOs (shared with UART TX/RX ZYNQ-FTDI).
- 1 Gbps RGMII Ethernet interface.
- High Speed USB 2.0 ULPI with full OTG support.
- High Speed USB 2.0 to UART/JTAG interface, including microUSB-B connector.
- microSD™
- JTAG
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Main Components
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Configuration Signals
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UART Interface
The TE0716 provides UART access to the TE0716 SoM through B2B connector JP1. The TE0716 is also provided equipped with a FTDI USB-to-UART adapter connected to the MicroUSB connector J13, but ONLY ONE connection for UART should be used at the time! (please read "Notes" in the following table). The UART interface is connected to the Zynq UART PS (UART 0).
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USB Interface
@Guillermo: Hier die JP2 Stecker Pins wo USB rausgeführt wird
ETH Interface
@Guillermo: Hier die JP11 Stecker Pins wo ETH rausgeführt wird
ADC Interface
The analog inputs of the ADCs are connected to B2B connector JP1The TE0716 provides USB access to the TE0716 SoM through B2B connector JP2. The USB interface is connected later to the Zynq UART PS (USB 0), by using a USB PHY.
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ADC
JP1-106..107 | SAR ADC, U1.
ADC1
SAR ADC, U3. ADC2_P | ADC2_N JP1-109..110 | SAR ADC, U10.
ADC3SAR ADC, U15.
JP1-49..50 |
ADC4_N JP1-112..113 | SAR ADC, U17. ADC5_P | ADC5_N JP1-52..53 | SAR ADC, U2. ADC6_P | ADC6_N JP1-115..116 | SAR ADC, U4. ADC7_P | ADC7_N JP1-55..56 | SAR ADC, U11. ADC8_P | ADC8_N JP1-118..119 | SAR ADC, U16. ADC9_P | ADC9_N JP1-58..59 | SAR ADC, U19. |
PWM Interface
@Guillermo: Hier die JP2 Stecker Pins wo PWN rausgeführt wird
Micro USB -JTAG/UART
@Guillermo: Hier kurz erklären das UART JTAG über FTDI möglich ist und Hinweis das JTAG auch auf B2B J2 geht und nur einer JTAG bedienen darf
Micro SD Socket
A microSD™ card connector (J2) is connected via U35 (SD/SDIO Multiplexer - Level Translator) to PS (Bank-501). It is a Push-On/Push-Off socket type, and work with a voltage level of 3.3V.
MIO Pins
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Example:
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ETH Interface
The TE0716 provides ETH access to the TE0716 SoM through B2B connector JP1. The ETH interface is connected later to the Zynq Ethernet PS (Ethernet 0), by using a ETH PHY.
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ADC Interface
The analog inputs of the ADCs are connected to B2B connector JP1.
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SPI_CS , SPI_DQ0... SPI_DQ3
SPI_SCK
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PS MIO banks 500/501 signal connections to interface.
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MIO Pin | Connected to
SPI-CS , SPI-DQ0... SPI-DQ3 SPI-SCK - | QSPI Flash, U7 | 11..13 | LED1_R..G..B | - | LED D4 | 14, 15 | UART_RX_ZYNQ, UART_TX_ZYNQ | JP1 | 3.3V Voltage level. Also Connected to U36-2. To use this signal from B2B connector, "UART_OB_DISABLE" (JP1-11) must be "High". | 16..27 | ETH-TXCK, ETH-TXD0..ETH-TXD3, ETH-TXCTL, ETH-RXCK, ETH-RXD0..ETH-RXD3, ETH-RXCTL | - | Gigabit ETH Transceiver, U8 | 28..39 | OTG-DATA0..OTG-DATA7, OTG-DIR, OTG-STP, OTG-NXT, OTG-CLK | - | USB 2.0 ULPI transceiver, U18 | 40..45 | PS_SD_CLK, PS_SD_CMD, PS_SD_DAT0..PS_SD_DAT3 | J2 | 3.3V Voltage level. Connected to PS via U35 (SD/SDIO Multiplexer - Level Translator) | 46, 47 | I2C_SCL, I2C_SDA | - | General Purpose EEPROM, U21 | MAC EEPROM, U24 51 | PHY-RST | - | Gigabit ETH Transceiver, U8 | USB 2.0 ULPI transceiver, U18 52, 53 | ETH-MDC, ETH-MDIO | - | Gigabit ETH Transceiver, U8 | |
Test Points
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PWM Interface
The PWM signals are connected to B2B connector JP2. All this digital signals are connected to PL Bank 33 (except for PWM_6_H and PWM_6_L which are connected to PL Bank 13). These signals could be also used as normal single ended I/Os.
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Micro USB -JTAG/UART
A microUSB-B connector (J13) is connected to the FTDI. It provides the ability to communicate to the PL FPGA via JTAG, as well as to the PS UART (UART 0).
Caution: because the TE0716 also provides UART and JTAG access to the FPGA through B2B connectors JP1 and JP2 respectively, ONLY ONE connection for UART, and ONLY ONE connection for JTAG, should be used at the time! (please read "UART Interface" and "JTAG Interface" above in the "Board to Board (B2B)" Section).
Micro SD Socket
A microSD™ card connector (J2) is connected via U35 (SD/SDIO Multiplexer - Level Translator) to Zynq PS (Bank501/SDIO 0). It is a Push-On/Push-Off socket type, and work with a voltage level of 3.3V.
MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example:
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PS MIO banks 500/501 signal connections to interface.
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Test Points
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On-board Peripherals
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE0716 module has two 500MByte DDR3L SDRAM chips (U12 & U13) fully connected to PS DDR BANK 502, and arranged into 32-bit wide memory bus providing total on-board memory size of 1GByte.
- Configuration: 256Mx16*
- Supply voltage: 1.35V (1.5V tolerant).
- Speed: 1.25ns @ CL11 (DDR3-1600)*
- Temperature: Industrial Range -40°C to +95°C Tcase.
Notes: * standard value but depends on assembly version.
Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
On-board 32MByte QSPI flash memory S25FL256S (U7) could be used to store the initial FPGA configuration file. After configuration completes, the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
- Part number: S25FL256SAGBHI20*
- Supply voltage: 3.3V (2.7V - 3.6V).
- Speed: 133MHz max.*
- Temperature: Industrial Range -40°C to +85°C.
Notes: * standard number/value but depends on assembly version.
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EEPROM
There are 2x EEPROMs sharing the same I2C bus (I2C interface is connected to the Zynq I2C PS (I2C 0).:
MAC-Address EEPROM
A 2Kbit 24AA025E48 serial EEPROM I2C memory (U24), connected to the BANK501 PSMIOs, contains a globally unique 48-bit node address, which is compatible with EUI-48TM specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks, the upper half of the array (80h-FFh), stores the 48-bit node address and is permanently write-protected, while the other block is available for application use.
- Part number: 24AA025E48T-I/OT
- Supply voltage: 1.8V (1.7V - 5.5V).
- FCLK: 100KHz (@VCC=1.8V)
- Temperature: Industrial Range -40°C to +85°C.
General Purpose EEPROM
The TE0716 module has also a 512Kb Serial EEPROM I2C memory (U21).
- Part number: CAT24C512WI-GT3
- Supply voltage: 1.8V (1.8V - 5.5V).
- FCLK: 100KHz/400KHz/1MHz
- Temperature: Industrial Range -40°C to +85°C.
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ADCs
The TE0716 module has 10x 12-Bit Low Power SAR Analog-to-Digital Converter, fully differential input, signed output, with SPI−compatible interface (NCD98011), which are connected to the FPGA PL BANK34.
- Part number: NCD98011XMXTAG
- Analog supply and ADC reference voltage (VCC): 3.3V (1.65V – 3.6V).
- Digital I/O supply voltage (VDD): 3.3V (1.65V – 3.6V).
- Differential analog inputs: 1 per ADC.
- Full−Scale Analog Input Voltage Span: +VCC max Vppd, -VCC min Vppd, (VCM to VCC/2).
- Absolute Voltage Range Vinp or Vinn to GND: VCC + 0.1V
- Sampling rate: 2 MSPS max.
- SNR: 70dB @1KHz fIN.
- THD: -80dB @1KHz fIN.
- Junction Temperature: Range -40°C to +125°C.
All the analog inputs are connected to B2B JP1 as follows:
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All the digital signals are connected to PL Bank 34 as follows:
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Clock Sources
The TE0716 board is equipped with 4x Oscillators, every one with its specific function.
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U37, DC-DC Converter
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On-board Peripherals
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DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE0716 module has two 500MByte DDR3L SDRAM chips (U12 & U13) fully connected to PS DDR BANK 502, and arranged into 32-bit wide memory bus providing total on-board memory size of 1GByte.
- Configuration: 256Mx16*
- Supply voltage: 1.35V (1.5V tolerant).
- Speed: 1.25ns @ CL11 (DDR3-1600)*
- Temperature: Industrial Range -40°C to +95°C Tcase.
Notes: * standard value but depends on assembly version.
Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
On-board 32MByte QSPI flash memory S25FL256S (U7) could be used to store the initial FPGA configuration file. After configuration completes, the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
- Part number: S25FL256SAGBHI20
- Supply voltage: 3.3V (2.7V - 3.6V).
- Speed: 133MHz max.
- Temperature: Industrial Range -40°C to +85°C.
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EEPROM
There are 2x EEPROMs sharing the same I2C bus:
MAC-Address EEPROM
A 2Kbit 24AA025E48 serial EEPROM I2C memory (U24), connected to the BANK501 PSMIOs, contains a globally unique 48-bit node address, which is compatible with EUI-48TM specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks, the upper half of the array (80h-FFh), stores the 48-bit node address and is permanently write-protected, while the other block is available for application use.
- Part number: 24AA025E48T-I/OT
- Supply voltage: 1.8V (1.7V - 5.5V).
- FCLK: 100KHz (@VCC=1.8V)
- Temperature: Industrial Range -40°C to +85°C.
General Purpose EEPROM
- The TE0716 module has also a 512Kb Serial EEPROM I2C memory (U21).
- Part number: CAT24C512WI-GT3
- Supply voltage: 1.8V (1.8V - 5.5V).
- FCLK: 100KHz/400KHz/1MHz
- Temperature: Industrial Range -40°C to +85°C.
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I2C Address |
Notes | 2K Serial EEPROMs with EUI-48™ | 0xA6 (write) U24 | - | 512Kb Serial EEPROM | 0xA0 (write) U21 | - | |
ADCs
The TE0716 module has 10x 12-Bit Low Power SAR Analog-to-Digital Converter, fully differential input, signed output, with SPI−compatible interface (NCD98011), which are connected to the FPGA PL BANK34.
- Part number: NCD98011XMXTAG
- Analog supply and ADC reference voltage (VCC): 3.3V (1.65V – 3.6V).
- Digital I/O supply voltage (VDD): 3.3V (1.65V – 3.6V).
- Differential analog inputs: 1 per ADC.
- Full−Scale Analog Input Voltage Span: +VCC max Vppd, -VCC min Vppd, (VCM to VCC/2).
- Absolute Voltage Range Vinp or Vinn to GND: VCC + 0.1V
- Sampling rate: 2 MSPS max.
- SNR: 70dB @1KHz fIN.
- THD: -80dB @1KHz fIN.
- Junction Temperature: Range -40°C to +125°C.
All the analog inputs are connected to B2B JP1 as follows:
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Ethernet
The TE0716 is provided the on-board Gigabit Ethernet PHY Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the Zynq Ethernet PS (Ethernet 0).
- Part number: 88E1512-A0-NNP2I000
- Supply voltage: 1.8V and 3.3V.
- Reference clock: 25.00MHz
- Temperature: Industrial Range -40°C to +85°C.
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Designator
Schematic | B2B JP1 pin | Notes | U1 | ADC0_P | ADC0_N 106 - 107 | 3.3V Max Voltage on any pin. U2 | ADC5_P 52 - 53 | 3.3V Max Voltage on any pin. | U3 | ADC1_P 46 - 47 | 3.3V Max Voltage on any pin. | U4 | ADC6_P 115 - 116 | 3.3V Max Voltage on any pin. | U10 | ADC2_P 109 - 110 | 3.3V Max Voltage on any pin. | U11 | ADC7_P 55 - 56 | 3.3V Max Voltage on any pin. | U15 | ADC3_P 49 - 50 | 3.3V Max Voltage on any pin. | U16 | ADC8_P 118 - 119 | 3.3V Max Voltage on any pin. | U17 | ADC4_P 112 - 113 | 3.3V Max Voltage on any pin. | U19 | ADC9_P 58 - 59 | 3.3V Max Voltage on any pin. | |
All the diigital signals are connected to PL Bank 34 as follows:
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USB 2.0 ULPI transceiver
USB3320 is a Hi-Speed USB 2.0 Transceiver that provides a configurable physical layer (PHY) solution with full OTG support. The USB PHY ULPI interface is connected to the Zynq USB PS (USB 0).
- Part number: USB3320C-EZK
- Supply voltage: 1.8V and 3.3V.
- Reference clock: 52.00MHz
- Temperature: Industrial Range -40°C to +85°C.
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Clock Sources
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Designator |
Frequency |
MHz | - | U9 | Ethernet PHY Reference Clock Input | 25MHz | - | U14 | Ethernet PHY Reference Clock Input | 52MHz | - | U41 | MHz | - | |
Ethernet
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FTDI USB 2.0 to UART/JTAG
The TE0716 board is equipped with the FTDI FT2232H USB 2.0 to JTAG/UART adapter controller connected to the MicroUSB 2.0 B connector J13 to provide JTAG and UART access to the attached module.
There is also a 4Kbit configuration EEPROM U40 (M93C66) wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools. Refer to the FTDI datasheet to get information about the capacity of the FT2232H chip.
ATTENTION!: Do not access the FT2232H EEPROM using FTDI programming tools. By doing it, you could erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license, the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.
Channel A of the FTDI chip is configured as JTAG interface connected to the BANK 0 Zynq SoC.
Channel B can be used as UART interface through the 2-Bit Bus Switch (U36), which routes to the BANK 500 Zynq SoC, when the Output of the Bus Switch is Enable, and is available for other user-specific purposes. Caution: UART is also routed to the B2B JP1 connector, but ONLY ONE connection for UART should be used at the time!.
- Part number: FT2232H-56Q
- Supply voltage: 3.3V (3.0V - 3.6V).
- Reference clock: 12.00MHz
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TX_CLK
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RGMII Transmit Clock
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TXD[0..3]
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RGMII Transmit Data
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TX_CTRL
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RGMII Transmit Control
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RX_CLK
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RGMII Receive Clock
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RXD[0..3]
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RGMII Receive Data
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RX_CTRL
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RGMII Receive Control
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MDC
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Management data clock reference
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MDIO
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Management data
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RESETn
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Hardware reset. Active low.
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MDIP[0..3] MDIN[0..3]
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Media Dependent Interface
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XTAL_IN
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Reference Clock Input
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LED[0..1]
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LED output
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USB 2.0 ULPI transceiver
USB3320 is a Hi-Speed USB 2.0 Transceiver that provides a configurable physical layer (PHY) solution with full OTG support.
- Part number: USB3320C-EZK
- Supply voltage: 1.8V and 3.3V.
- Temperature: Industrial Range -40°C to +85°C.
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CLKOUT | OTG-CLK | MIO36 | ULPI Output Clock | - | |
DATA[0..3] | OTG-DATA0..3 | MIO32..35 | ULPI bi-directional data bus | - | |
DATA[4] | OTG-DATA4 | MIO28 | ULPI bi-directional data bus | - | |
DATA[5..7] | OTG-DATA5..7 | MIO37..39 | ULPI bi-directional data bus | - | |
DIR | OTG-DIR | MIO29 | Controls the direction of the data bus | - | |
STP | OTG-STP | MIO30 | terminates transfers PHY input | - | |
NXT | OTG-NXT | MIO31 | control data flow into and out of the PHY | - | |
RESETB | PHY-RST | MIO51, U8 | reset and suspend the PHY. Active low. | Shared with U8 (RESETn) Ethernet | |
DP | USB_OTG_D_P | JP2-64 | D+ pin of the USB cable | 3.3V Voltage level | |
DM | USB_OTG_D_N | JP2-65 | D- pin of the USB cable | 3.3V Voltage level | |
ID | USB_OTG_ID | JP2-66 | ID pin of the USB cable | 3.3V Voltage level | |
CPEN | USB_VBUS_EN | JP2-67 | Controls the external VBUS power switch | 3.3V Voltage level | |
VBUS | USB_VBUS | JP2-68 | For RVBUS connection | Max. voltage: 5.5V | |
REFCLK | OTG-RCLK | U14 | ULPI clock input | see also Clock Sources section |
FTDI USB 2.0 to UART/JTAG
The TE0716 board is equipped with the FTDI FT2232H USB 2.0 to JTAG/UART adapter controller connected to the MicroUSB 2.0 B connector J13 to provide JTAG and UART access to the attached module.
There is also a 4Kbit configuration EEPROM U40 (M93C66) wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools. Refer to the FTDI datasheet to get information about the capacity of the FT2232H chip.
Do not access the FT2232H EEPROM using FTDI programming tools. By doing it, you could erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license, the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.
Channel A of the FTDI chip is configured as JTAG interface connected to the BANK 0 Zynq SoC.
Channel B can be used as UART interface routed to the 2-Bit Bus Switch, which routes to the BANK 500 Zynq SoC, when the Output of the Bus Switch is Enable, and is available for other user-specific purposes.
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| U?? Pin | Signal Name | Connected to | Signal Description | Note |
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
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Power Supply
Power supply with minimum current capability of 3.0 A (TBD*) for system startup is recommended.
* TBD - To Be Determined
Power Consumption
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| S1 | B34_L14_P (SW1) | Low | User | - | ||||||||||||||
| S2 | B34_L14_N (SW2) | Low | User | - | ||||||||||||||
| S3 | U26-MR (nRST) | Low | Reset (PS_POR_B) | see also Reset Process section in Configuration Signals |
Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
- Power on-sequence
- Power distribution
- Voltage monitoring circuit
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For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" . |
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* TBD - To Be Determined
Power Distribution Dependencies
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Power-On Sequence
The TE0716 has only one common "PGOOD" signal (from U37, U43, U45 and U46), and there is no Enable for the board. You could control the startup of the board IC, by controlling the +5.0V and the +5.0V_VAA input signals only.
Power Supply
Power supply with minimum current capability of 3.0 A (TBD) for system startup is recommended.
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| +5.0V_VAA | less than 250mA (TBD) |
* TBD - To Be Determined
Power Distribution Dependencies
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Voltage Monitor Circuit
The TE0716 has also a Voltage Monitor IC. It keeps nRST signal low if the FPGA core voltage (+1.0V) drops under 0.84V or the 3.3V power supply drops to 2.94V or less.
Power Good signal is unique and comes from the power supplies IC U37, U43, U45 and U46, as you can see in the previous section "Power-On Sequence", and also could make nRST to remain low until PGOOD is high.
See also "Reset process." section in "Configuration Signals" for additional information.
Power-On Sequence
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Power Rails
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Symbols | Description | Min | Max | Unit | V | V | V | V | V | V | V | V |
Recommended Operating Conditions
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Physical Dimensions
Module size: 45 mm × 65 mm. Please download the assembly diagram for exact numbers.
Mating height with 61982 receptacle connectors: 5mm, 7mm, 13mm and 17mm stack heights.
PCB thickness: 1.65 mm.
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Currently Offered Variants
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Set correct link to the shop page overview table of the product on English and German. Example for TE0706: ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706TE0716 DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706TE0716 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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Document Change History
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Overview
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