Page History

SmartDesign components

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HTML

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<style>
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  width: 100% !important;
  max-width: 1200px !important;
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Important General Note:

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Export PDF to download, if vivado revision is changed!

Custom_table_size_100

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Important General Note:

Export PDF to download, if Libero or SoftConsole revision is changed!

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template (note: inner scroll ignore/only with drawIO object):

Scroll Title

anchor	Figure_xyz
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, use

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

...

Create DrawIO object here: Attention if you copy from other page, use

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

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Table template:

Layout macro can be use for landscape of large tables
Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

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anchor	Table_xyz
title	Text

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Overview

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Notes :

short description of the design
Short Link of "Scroll only" macro:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

This demo is a Webserver

...

tem0002-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

Add basic key futures, which can be tested with the design

Excerpt
Libero 12.

...

Real Time Clock

Revision History

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Notes :

add every update file on the download
add design changes on description
Datum & Ordnernamen UPDATEN / CHECKEN

Scroll Title

anchor	Table_DRH
title	Design Revision History

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Date	Libero	Project Built	Authors	Description
2020-

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Ported from 11.8

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Initial release

Release Notes and Know Issues

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Notes :

add known Design issues and general notes for the current revision
do not delete known issue, add fixed version time stamp if issue fixed

Scroll Title

anchor	Table_KI
title	Known Issues

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
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cellHighlighting	true

Issues	Description	Workaround/Solution	To be fixed version

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Requirements

Software

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Notes :

list of software which was used to generate the design

Scroll Title

anchor	Table_SW
title	Software

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cellHighlighting	true

Software	Version	Note

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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

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anchor	Table_HWM
title	Hardware Modules

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Module Model	Board Part Short Name	PCB Revision Support	DDR	embedded SRAM

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<<============== ABKLÄREN OB BEIDE HW-Revisionen unterstütz werden

Note: Design contains also Board Part Files for TE0808 only configuration, this boart part files are not used for this reference design.

Additional HW Requirements:

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anchor	Table_AHW
title	Additional Hardware

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Additional Hardware	Notes
Demo host computer	Demo was created and tested on windows

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archive "TEM0002-SmartBerry_Webserver-Demo_Libero-X.y_Datum-Time":

Design Sources

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title	Design sources

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Type	Location	Notes
Libero

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Additional Sources

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anchor	Table_ADS
title	Additional design sources

Prebuilt

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Notes :

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anchor	Table_PF
title	Prebuilt files

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File

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File-Extension

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Description

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Debian SD-Image

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*.img

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Debian Image for SD-Card

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MCS-File

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*.mcs

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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

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MMI-File

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*.mmi

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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

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SREC-File

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*.srec

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Converted Software Application for MicroBlaze Processor Systems

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anchor	Table_PF
title	Prebuilt files (only on ZIP with prebult content)

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File

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File-Extension

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Description

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Download

Reference Design is only usable with the specified Libero/SoftConsole version. Do never use different versions of Microsemi Software for the same Project.

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Important set new Vivado version link on every Design update of new vivado version!
Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

Reference Design is available on:

TEM0002 "Webserver Demo" Reference Design <<================ ADD / Convert to - LINK

Preparations

The reference design is available as a prebuild zip archieve, which contains the hard & soft -ware project folders and the board configuration file "microsemi-smartfusion2-smartberry-ddr.cfg" . It was created and tested in windows environment.

The zip archieve must to be extracted. The board configuration file needs to copied into your SoftConsole installation directory. When taking the required SoftConsole version into account, SoftConsole version 6.2, and the default installation path, copy the board configuration file into:
"C:\Microsemi\SoftConsole_v6.2\openocd\share\openocd\scripts\board\"

Connecet the board via usb cable to your demo host computer.

Connect the boards ethernet port to your demo host computer. The demo is confiured to establish a network connection via the DHCP protocol, therefore a free router / network port can be used.
A direct port to port connection between the demo host computer and the board is also possible but requires to reconfigure the software project.

Hardware design flashing

Program the FPGA

---------------------------------------------------------------------------------------------------

// File to Programm is under:
// C:\temp\TEM0002-01\Smartberry_Webserver_Demo\LiberoProject\Smartberry_Webserver\designer\SB\export\SD.dat

...

Start, in the left part of the start page > Open... , point to:
C:\temp\TEM0002-01\LiberoProject_updated\Smartberry_Webserver\Smartberry_Webserver.prjx

Now, one could update outdated Ip-Cores:
In newly opened window "New cores are available" > Klick Dismiss

Automatically set ********************************************************

...

<zip archive>
/ Libero-X.y_Referenz-Design_XY

Libero Project containing the modules
Hardware Reference Design

SoftConsole

<zip archive>
      / Softconsole-X.y-Workspace
            / Smartberry_Hello_World_X.y
            / Smartberry_Webserver_X.y
            / Smartberry_Webserver_DDR_X.y

SoftConsole Workspace
contains the Software Projects :

Hello_World

and two variants of the Demo :

Smartberry_Webserver

SoftConsole

<zip archive>
/ Softconsole-X.y-Workspace
/ microsemi-smartfusion2-smartberry-ddr .cfg

Board configuration file, needed to

debug / run applications

Download

The Trenz Electronic Reference Designs and Demos are usable with the specified Microsemi Libero / SoftConsole version. Usage of a different Microsemi Libero / SoftConsole software versions is not recommended.

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Important set new Libero version link on every Design update of new Libero version!
Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

Reference Designs / Demos are available via the following link:

TEM0002_Reference Designs/Demos

The download is a ZIP compressed archive. Extract the archive before usage.

Design Flow

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Notes :

Basic Design Steps
Add/ Remove project specific description

The Hardware and Software Reference / Demo -Designs Projects are available as a prebuild zip archive. The archive contains a Libero Hardware Project and a SoftConsole Workspace folder, they were created and tested in windows environment.

This SoftConsole Workspace contains the Software Project Hello World and the Demo Webserver, the demo is offered in two variants. The board configuration file "microsemi-smartfusion2-smartberry-ddr.cfg" is required for the usage of the Software projects via the IDE SoftConsole.

Launch

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Programming and Startup procedure

Executing a Reference / Demo Design on a module requires the powering of it and a JTAG or UART Connection for Programming and Communication. Often the programming is a two fold process, where the first programming configures the FPGA and the second programming flashes Software code to be executed inside the FPGA / ARM processor.

Connecting

Connect the modules micro USB connector to your host pc, this enables the powering of the module and a simultaneous JTAG and UART connection .

Only necessary for running the Demo Webserver:
The demo is configured to establish a network connection via the DHCP protocol, therefore, if a a free router port is used, no further port setup is required.
If a "direct Ethernet Connection" between Host PC and module is used, the user must know how to setup this connection type. Further down in this chapter is explained how to setup the Demo Webserver and recompile it, so that it uses a static IP.

Driver check

When the module is connected via USB cable to your demo host computer, in the Windows Device Manager appear the following tree board driver related devices:

In section Ports (COM & LPT):

FlashPro5 Port (ComX)

In section Universal Serial Bus controllers:

USB FP5 Serial Converter A
USB FP5 Serial Converter B

The Device Manager is accessible via "Right mouse click context menu" from the Windows Start Menu Button. When these devices are not visible, the driver installation through libero could be faulty.

Programming the Hardware design

Programming of the Hardware reference Design requires to open the FPGA Design IDE Libero

Scroll Title

anchor	Figure_1
title	Libero GUI "Run PRGORAMM ACTION"

Image Added

The Hardware Reference Design can be opened via "Project > Open Project" in the top right corner of Libero (picture above - upper green rectangle). A file dialogue opens, point the dialogue along the extracted download to the folder containing the Hardware Reference Design.

Disk :\ Path-to-the-Demo-archive \ Extracted ZIP-archive \ Libero-X.y_Referenz-Design\

Double left mouse click onto the project file "Referenz-Design_XY .prjx" to open it. The board is automatically selected and setup to be flashed by Libero.

In the upper left section of Libero, select the tab "Design Flow" (picture above - lover green rectangle) and flash it to the board via "Program Design > and double left mouse click onto "Run PROGRAM Action" (picture above - row with blue background).

Warnings should not affect the functionality of a Reference / Demo -Design.

UART connection

Before flashing any Software Project to the module, open a comport terminal to the boards comport, so that it's messages can be captured.

Programming a Software project

Open SoftConsole and press "Browse..." near the right edge. A file dialogue opens, point the dialogue along the extracted download to the folder containing the SoftConsole Workspace.

Disk :\ Path-to-the-Demo-archive \ Extracted ZIP-archive \ Softconsole-X.y-Workspace \

Confirm your selectioin by pressing "Ok" , the dialogue closes, and open The SoftConsole by pressing "Launch"

Scroll Title

anchor	Figure_2
title	SoftConsole "Select the Workspace"

Image Added

Subsequently the program opens and shows the software project's who are contained inside the workspace to the left, under "Project Explorer".

Scroll Title

anchor	Figure_3
title	SoftConsole GUI

Image Added

To simply run a Project, press the triangle right to the button marked with a "R" in the picture above and select a variant of the demo.

Pressing the triangle next to the button marked with "D" let you select which variant to be executed in debug mode.

Debug controls - Resume - Pause - Stop

Scroll Title

anchor	Figure_4
title	SoftConsole "Debug controlls"

Image Added

Switch between Debug and Run perspective (upper right corner program window)

Scroll Title

anchor	Figure_5
title	SoftConsole "Switch GUI layout"

Image Added

System Design - Libero

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Description of Block Design, Constrains... BD Pictures from Export...

Smart Design

Scroll Title

anchor	Figure_BD
title	Block Design

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Constrains

Code Block

language	ruby
title	user.pdc
linenumbers	true
collapse	true

# Microsemi I/O Physical Design Constraints file

# User I/O Constraints file 

# Version: v12.4 12.900.0.16

# Family: SmartFusion2 , Die: M2S010 , Package: 400 VF

# Date generated: Mon Nov 16 11:11:16 2020 


# 
# User Locked I/O Bank Settings
# 


# 
# Unlocked I/O Bank Settings
# The I/O Bank Settings can be locked by directly editing this file
# or by making changes in the I/O Attribute Editor
# 


# 
# User Locked I/O settings
# 

set_io Eth_LED1A \
-pinname Y10 \
-fixed yes \
-DIRECTION OUTPUT


set_io Eth_LED1B \
-pinname U12 \
-fixed yes \
-DIRECTION OUTPUT


set_io Eth_LED2A \
-pinname V14 \
-fixed yes \
-DIRECTION OUTPUT


set_io Eth_LED2B \
-pinname U14 \
-fixed yes \
-DIRECTION OUTPUT


set_io GLED \
-pinname G17 \
-fixed yes \
-DIRECTION OUTPUT


set_io GPIO_5_F2M_taster_S4 \
-pinname E17 \
-fixed yes \
-DIRECTION INPUT


set_io GPIO_6_F2M_taster_S5 \
-pinname E16 \
-fixed yes \
-DIRECTION INPUT


set_io MAC_GMII_MDC \
-pinname N1 \
-fixed yes \
-iostd LVCMOS15 \
-DIRECTION OUTPUT


set_io PHY_LED0 \
-pinname U11 \
-fixed yes \
-DIRECTION INPUT


set_io PHY_LED1 \
-pinname T14 \
-fixed yes \
-DIRECTION INPUT


set_io PHY_MDIO \
-pinname N2 \
-fixed yes \
-iostd LVCMOS15 \
-DIRECTION INOUT


set_io {PHY_RD[0]} \
-pinname K5 \
-fixed yes \
-iostd LVCMOS15 \
-DIRECTION INPUT


set_io {PHY_RD[1]} \
-pinname H1 \
-fixed yes \
-iostd LVCMOS15 \
-DIRECTION INPUT


set_io {PHY_RD[2]} \
-pinname H2 \
-fixed yes \
-iostd LVCMOS15 \
-DIRECTION INPUT


set_io {PHY_RD[3]} \
-pinname J4 \
-fixed yes \
-iostd LVCMOS15 \
-DIRECTION INPUT


set_io PHY_RESETN \
-pinname R13 \
-fixed yes \
-DIRECTION OUTPUT


set_io PHY_RX_CTL \
-pinname K1 \
-fixed yes \
-iostd LVCMOS15 \
-DIRECTION INPUT


set_io {PHY_TD[0]} \
-pinname L1 \
-fixed yes \
-iostd LVCMOS15 \
-DIRECTION OUTPUT


set_io {PHY_TD[1]} \
-pinname M2 \
-fixed yes \
-iostd LVCMOS15 \
-DIRECTION OUTPUT


set_io {PHY_TD[2]} \
-pinname M1 \
-fixed yes \
-iostd LVCMOS15 \
-DIRECTION OUTPUT


set_io {PHY_TD[3]} \
-pinname M3 \
-fixed yes \
-iostd LVCMOS15 \
-DIRECTION OUTPUT


set_io PHY_TX_CTL \
-pinname K3 \
-fixed yes \
-iostd LVCMOS15 \
-DIRECTION OUTPUT


set_io RGB_B \
-pinname H6 \
-fixed yes \
-DIRECTION OUTPUT


set_io RGB_G \
-pinname F6 \
-fixed yes \
-DIRECTION OUTPUT


set_io RGB_R \
-pinname H5 \
-fixed yes \
-DIRECTION OUTPUT


set_io RLED \
-pinname G16 \
-fixed yes \
-DIRECTION OUTPUT


set_io RXC \
-pinname J2 \
-fixed yes \
-iostd LVCMOS15 \
-DIRECTION INPUT


set_io TXC \
-pinname K7 \
-fixed yes \
-iostd LVCMOS15 \
-DIRECTION OUTPUT



# 
# Dedicated Peripheral I/O Settings
# 


# 
# Unlocked I/O settings
# The I/Os in this section are unplaced or placed but are not locked
# the other listed attributes have been applied
# 


#
#Ports using Dedicated Pins

#

set_io DEVRST_N \
-pinname U17 \
-DIRECTION INPUT

Software Design - SoftConsole

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Note:

optional chapter separate
sections for different apps

Application

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----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2019.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

Modified Files: blconfig.h, bootloader.c
Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2019.2 xilisf_v5_11

Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 2019.2 FSBL

General:

Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device ID

Module Specific:

Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

Modified Files: main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2019.2 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device Name

Module Specific:

Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Demo - Webserver_...

The demo projects "Smartberry_Webserver_X.y" and "Smartberry_Webserver_DDR_X.y" are identical variants of the demo, they only differ in their memory location:

Smartberry_Webserver_X.y - Application code is stored to the FPGA's embedded non-volatile memory (eNVM)
Smartberry_Webserver_DDR_X.y - Application code is stored to the FPGA's external volatile memory (DDR3/L SDRAM) and lost during power down

UART output:

Scroll Title

anchor	Figure_6
title	COM-port Terminal Webserver "Welcome / IP -message"

Image Added

Static IP configuration

Scroll Title

anchor	Figure_7
title	SoftConsole "main.c - Set IP"

Image Added

To disengaging the DHCP mode one has to setup up an IP and Gateway Address in the code unit "main.c" roughly at line 270. Alternativly, the demo hosts IP Address can be changed.

Furthermore the corresponding compiler flag needs to be deleted in the project setting. To do so, in the "Project Explorer" tab, right mouse click onto the project and select Properties in the appearing menu.

Scroll Title

anchor	Figure_8
title	SoftConsole "Static IP- Change Defines""

Image Added

In the left section of the properties window select "C/C++ Build > Settings" in the right section select the tab "Tool Settings > GNU ARM Cross C Compiler > Preprocessor" under "Defined symbols (-D)" delete the compiler flag "NET_USE_DHCP" and press "Apply". Confirm the following dialogue and press "Cancel".

Lastly, the project needs to be recompiled. In the top menu of the SoftConsole select "Project > Build ALL / Build Project".

Warnings should not affect the demo. can be ignored.

Reference Design - HelloWorld_...

Hello World example as endless loop instead of one console output. Each loop lights up each LED. The user buttons responds with a message at any time.

UART output:

Scroll Title

anchor	Figure_9
title	COM-port Terminal "Hello World loop"

Image Added

Automatically set END ****************************************************

On the left, in section Design Flow,
point "Program Design" double click "Run PROGRAM Action" to program the Design

?!?!?!?
Warnings Core 'Actel: ... ' is missing can be ignored,
because the target file:
PPD file 'C:/temp/TEM0002-01/LiberoProject_updated/Smartberry_Webserver/designer/SB/SB.ppd' has been loaded
is included and allready compiled.

Software project flashing

Design Flow

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Notes :

Basic Design Steps
Add/ Remove project specific description

Note
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

~~Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.~~

~~See also:~~

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

~~_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:~~
Image Removed
~~Press 0 and enter to start "Module Selection Guide"~~
~~(optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)~~
~~Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process)~~
1. ~~(optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"~~
  ~~Note: Select correct one, see alsoTE Board Part Files~~
  1. ~~Important: Use Board Part Files, which ends with *_tebf0808~~
~~Create XSA and export to prebuilt folder~~
1. ~~Run on Vivado TCL: TE::hw_build_design -export_prebuilt~~
  ~~Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder~~
~~Create Linux (bl31.elf, uboot.elf , Image and system.dtb) with exported XSA~~
1. ~~XSA is exported to "prebuilt\hardware\<short name>"~~
  ~~Note: HW Export from Vivado GUI create another path as default workspace.~~
2. ~~Create Linux images on VM, see PetaLinux KICKstart~~
  1. ~~Use TE Template from /os/petalinux/~~
  2. ~~Execute the script file for Debian/Ubuntu~~
~~Add Linux files (bl31.elf, uboot.elf , Image and system.dtb) to prebuilt folder~~
1. ~~"prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"~~
~~Generate Programming Files with Vitis~~
1. ~~Run on Vivado TCL: TE::sw_run_vitis -all~~
  ~~Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"~~
2. ~~(alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis~~
  ~~Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis~~
~~Preparing SD card for SD Filesystem and hard disk for HD Filesystem → See Programming section~~

Launch

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Note:

Programming and Startup procedure

For basic board setup, LEDs... see: TEBF0808 Getting Started

Programming

Note
Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
Press 0 and enter to start "Module Selection Guide"
1. Select assembly version
2. Validate selection
3. Select Create and open delivery binary folder
  Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Not used in this example.

SD

Format the SD Card with SD Card Formatter or other tool
Write the Debian image or Ubuntu image file on SD Card with Win32DiskImager
It will automatically in BOOT directory two DTB file generated
1. system_sd.dtb : This file ist used , if the root file system is located on SD card.
2. system_harddisk.dtb : This file ist used , if the root file system is located on hard disk.
3. Note: To use one of the DTB files, this file must be renamed to system.dtb
Rename the system_sd.dtb file in BOOT directory to system.dtb
Copy Petalinux Image (not use image.ub), system.dtb and Boot.bin files on SD-Card.
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

Prepare HW like described on section TE0808 StarterKit#Programming
Connect UART USB (JTAG XMOD)
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Note: See TRM of the Carrier, which is used.
(Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
(Optional) Connect Sata Disc
(Optional) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
(Optional) Connect Network Cable
Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from SD into OCM, 2. FSBL loads ATF(bl31.elf) and U-boot from SD/QSPI into DDR, 3. U-boot load Linux from SD into DDR.

Linux

Open Serial Console (e.g. putty)
1. Speed: 115200
2. COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
Linux Console:
Note: Wait until Linux boot finished For Linux Login use:
1. User Name: root
2. Password: root
You can use Linux shell now.
Debian Desktop
1. Use connected mouse + keyboard for interaction with GUI
2. Start the GUI with the command : startx
3. Web Browser Dillo open console and type dillo or use browser
4. open console and start video or audio with "mplayer <video or audio file>"
Ubuntu Desktop
1. Use connected mouse + keyboard for interaction with GUI
2. Start the GUI with the command : startx
3. Web Browser Mozilla firefox can be used.
4. Audio or Vider file can also be performed directly in GUI

Hard Disk (optional)

To locate root file system on Hard disk:

Plug in SD Card that you have prepared mit root file system
Plug in Hard Disk in Sata port on the carrier board
Format the hard disk by the following command:
1. mkfs.ext4 /dev/sda
Edit the fstab file in directory /etc/ to mount hard disk by the following commands:
1. mkdir /media/harddisk
2. nano /etc/fstab
3. Add this line to the fstab file and save it : /dev/sda /media/harddisk/ defaults 0 3
4. Reboot
Copy entire root file system in direcroty ROOTFS from SD card to hard disk by the following commands:
1. cd /media/ROOTFS
2. cp -r ./ /media/harddisk
Edit the fstab file in directory /media/harddisk/etc/ by the following commands and save it:
1. nano /media/harddisk/etc/fstab
2. Edit this line to the fstab file : /dev/sda /media/harddisk/ defaults 0 1
3. Comment this line: #/dev/mmcblk1p2 /media/ROOTFS defaults 0 1
Shutdown the system
Format the SD card
Rename the Device Tree Blob file system_harddisk.dtb to system.dtb
Copy the following files to SD Card:
1. Image
2. BOOT.bin
3. system.dtb
Plug in the SD Card and turn on the system

Vivado Hardware Manager

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Note:

Add picture of HW Manager
add notes for the signal either groups or topics, for example:
Control:
- add controllable IOs with short notes..
Monitoring:
- add short notes for signals which will be monitored only
SI5338_CLK0 Counter:
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

System Design - Vivado

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id	Comments

Note:

Description of Block Design, Constrains... BD Pictures from Export...

Block Design

Scroll Title

anchor	Figure_BD
title	Block Design

Image Removed

PS Interfaces

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Note:

optional for Zynq / ZynqMP only
add basic PS configuration

Activated interfaces:

...

anchor	Table_PSI
title	PS Interfaces

...

Constrains

Basic module constrains

Code Block

language	ruby
title	_i_bitgen.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Code Block

language	ruby
title	_i_io.xdc


#System Controller IP
  #LED_HD SC0 J3:31
  #LED_XMOD SC17 J3:48 
  #CAN RX SC19 J3:52 B47_L2_P in
  #CAN TX SC18 J3:50 B47_L2_N out 
  #CAN S  SC16 J3:46 B47_L3_N out
set_property PACKAGE_PIN J14 [get_ports BASE_sc0]
set_property PACKAGE_PIN G13 [get_ports BASE_sc5]
set_property PACKAGE_PIN J15 [get_ports BASE_sc6]
set_property PACKAGE_PIN K15 [get_ports BASE_sc7]
set_property PACKAGE_PIN A15 [get_ports BASE_sc10_io]
set_property PACKAGE_PIN B15 [get_ports BASE_sc11]
set_property PACKAGE_PIN C13 [get_ports BASE_sc12]
set_property PACKAGE_PIN C14 [get_ports BASE_sc13]
set_property PACKAGE_PIN E13 [get_ports BASE_sc14]
set_property PACKAGE_PIN E14 [get_ports BASE_sc15]
set_property PACKAGE_PIN A13 [get_ports BASE_sc16]
set_property PACKAGE_PIN B13 [get_ports BASE_sc17]
set_property PACKAGE_PIN A14 [get_ports BASE_sc18]
set_property PACKAGE_PIN B14 [get_ports BASE_sc19]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]

# PLL
#set_property PACKAGE_PIN AH6 [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}]
#set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}]
# Clocks
#set_property PACKAGE_PIN J8 [get_ports {B229_CLK1_clk_p[0]}]
#set_property PACKAGE_PIN F25 [get_ports {B128_CLK0_clk_p[0]}]
# SFP 
#set_property PACKAGE_PIN G8 [get_ports {B230_CLK0_clk_p}]
# B230_RX3_P
#set_property PACKAGE_PIN A4 [get_ports {SFP1_rxp}]
# B230_TX3_P
#set_property PACKAGE_PIN A8 [get_ports {SFP1_txp}]
# B230_RX2_P
#set_property PACKAGE_PIN B2 [get_ports {SFP2_rxp}]
# B230_TX2_P
#set_property PACKAGE_PIN B6 [get_ports {SFP2_txp}]

# Audio Codec
#LRCLK		  J3:49 B47_L9_N
#BCLK		    J3:51 B47_L9_P
#DAC_SDATA	J3:53 B47_L7_N
#ADC_SDATA	J3:55 B47_L7_P
set_property PACKAGE_PIN G14 [get_ports I2S_lrclk ]
set_property PACKAGE_PIN G15 [get_ports I2S_bclk ]
set_property PACKAGE_PIN E15 [get_ports I2S_sdin ]
set_property PACKAGE_PIN F15 [get_ports I2S_sdout ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ]
set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ]

Software Design - Vitis

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id	Comments

Note:

optional chapter separate
sections for different apps

For SDK project creation, follow instructions from:

Vitis

Application

...

hidden	true
id	Comments

----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2019.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

Modified Files: blconfig.h, bootloader.c
Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2019.2 xilisf_v5_11

Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 2019.2 FSBL

General:

Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device ID

Module Specific:

Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

Modified Files: main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2019.2 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device Name

Module Specific:

Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

SDK template in ./sw_lib/sw_apps/ available.

zynqmp_fsbl

TE modified 2019.2 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device Name

Module Specific:

Add Files: all TE Files start with te_*
- Si5345 Configuration
- OTG+PCIe Reset over MIO
- I2C MUX for EEPROM MAC

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

hello_te0808

Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Software Design - PetaLinux

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hidden	true
id	Comments

Note:

optional chapter separate
sections for linux
Add "No changes." or "Activate: and add List"

For PetaLinux installation and project creation, follow instructions from:

PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Select Image Packaging Configuration ==> Root filesystem type ==> Select SD Card

Changes:

CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""
# CONFIG_SUBSYSTEM_BOOTARGS_AUTO is not set
CONFIG_SUBSYSTEM_USER_CMDLINE="console=ttyPS0,115200 earlycon clk_ignore_unused earlyprintk root=/dev/mmcblk1p2 rootfstype=ext4 rw rootwait cma=1024M"
CONFIG_SUBSYSTEM_DEVICETREE_FLAGS=""
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_BOOTIMAGE_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_FLASH_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_SD_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_ETHERNET_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_IMAGE_NAME="system.dtb"
CONFIG_SUBSYSTEM_ENDIAN_LITTLE=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_FLASH_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_SD_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_ETHERNET_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_IMAGE_NAME="Image"

U-Boot

Start with petalinux-config -c u-boot
Changes:

CONFIG_ENV_IS_NOWHERE=y
# CONFIG_ENV_IS_IN_SPI_FLASH is not set
CONFIG_I2C_EEPROM=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SYS_I2C_EEPROM_BUS=2
CONFIG_SYS_EEPROM_SIZE=256
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0

Device Tree

Code Block

language	js

/include/ "system-conf.dtsi"
/ {
  chosen {
    	xlnx,eeprom = &eeprom;
		bootargs= "console=ttyPS0,115200 earlycon clk_ignore_unused earlyprintk root=/dev/mmcblk1p2 rootfstype=ext4 rw rootwait cma=1024M";
		/* notes: root=/dev/mmcblk1p2 for SD and root=/dev/sda for hard disk will be changed automatically by executing the debian/ubuntu script*/
  };
};

/* notes:
serdes: // PHY TYP see: dt-bindings/phy/phy.h
*/

/* default */

/* SD */

&sdhci1 {
	disable-wp;
	no-1-8-v;

};




/* USB  */


&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    snps,usb3_lpm_capable;
    snps,dis_u3_susphy_quirk;
    snps,dis_u2_susphy_quirk;
    phy-names = "usb2-phy","usb3-phy";
    phys = <&lane1 4 0 2 100000000>;
    maximum-speed = "super-speed";
};

/* ETH PHY */

&gem3 {
	phy-handle = <&phy0>;
	phy0: phy0@1 {
		device_type = "ethernet-phy";
		reg = <1>;
	};
};

/* QSPI */

&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};

/* I2C */

&i2c0 {
    i2cswitch@73 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x73>;
        i2c-mux-idle-disconnect;
        i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
        };
        i2c@1 { // SFP TEBF0808 PCF8574DWR
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
        };
        i2c@2 { // PCIe
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c@3 { // SFP1 TEBF0808
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
        i2c@4 {// SFP2 TEBF0808
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        };
        i2c@5 { // TEBF0808 EEPROM
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
            eeprom: eeprom@50 {
	            compatible = "atmel,24c08";
	            reg = <0x50>;
	          };
        };
        i2c@6 { // TEBF0808 FMC  
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;
        };
        i2c@7 { // TEBF0808 USB HUB
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <7>;
        };
    };
    i2cswitch@77 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x77>;
        i2c-mux-idle-disconnect;
        i2c@0 { // TEBF0808 PMOD P1
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
        };
        i2c@1 { // i2c Audio Codec
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
			/*
            adau1761: adau1761@38 {
                compatible = "adi,adau1761";
                reg = <0x38>;
            };
			*/
        };
        i2c@2 { // TEBF0808 Firefly A
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c@3 { // TEBF0808 Firefly B
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
        i2c@4 { //Module PLL Si5338 or SI5345
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        };
        i2c@5 { //TEBF0808 CPLD
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
        };
        i2c@6 { //TEBF0808 Firefly PCF8574DWR
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;
        };
        i2c@7 { // TEBF0808 PMOD P3
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <7>;
        };
    };
};

Kernel

Start with petalinux-config -c kernel

Changes:

CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)
CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)
CONFIG_EDAC_CORTEX_ARM64=y

Rootfs

Applications will be generated with Debian script or Ubuntu script (mkdebian_stretch.sh/mkubuntu_BionicBeaver.sh)

Applications

Applications will be generated with Debian script or Ubuntu script (mkdebian_stretch.sh/mkubuntu_BionicBeaver.sh)

Additional Software

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Note:

Add description for other Software, for example SI CLK Builder ...
SI5338 and SI5345 also Link to:
- Si5345
- Si5338

No additional software is needed.

SI5345

File location <design name>/misc/Si5345/Si5345-*.slabtimeproj

...

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision got to "Change History" of this page and select older document revision number.

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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

Scroll Title

anchor	Table_dch
title	Document change history.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths	2,,3,4
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Date

Document Revision

Authors

Description

Page info

...

Download Link update

2021-01-29

v.45

John Hartfiel

Link updates
table of content update

2020-11-24

v.41

Kilian Jahn

Libero12.4 release

--

all

Page info

infoType	Modified users
dateFormat	yyyy-MM-dd
type	Flat

--

Legal Notices

Include Page

	IN:Legal Notices
	IN:Legal Notices

Custom_fix_page_content

Scroll pdf ignore

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 7

New Version Current

Key

Table of contents

Overview

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Content

Design Sources

Additional Sources

Prebuilt

Download

Preparations

Hardware design flashing

Program the FPGA

Download

Design Flow

Launch

Connecting

Driver check

Programming the Hardware design

UART connection

Programming a Software project

System Design - Libero

Smart Design

Constrains

Software Design - SoftConsole

Application

scu

srec_spi_bootloader

xilisf_v5_11

zynq_fsbl

zynq_fsbl_flash

zynqmp_fsbl

zynqmp_fsbl_flash

zynqmp_pmufw

hello_te0820

u-boot

Demo - Webserver_...

Static IP configuration

Reference Design - HelloWorld_...

Software project flashing

Design Flow

Launch

Programming

Get prebuilt boot binaries

QSPI

SD

JTAG

Usage

Linux

Vivado Hardware Manager

System Design - Vivado

Block Design

PS Interfaces

Constrains

Basic module constrains

Software Design - Vitis

Application

scu

srec_spi_bootloader

xilisf_v5_11

zynq_fsbl

zynq_fsbl_flash

zynqmp_fsbl

zynqmp_fsbl_flash

zynqmp_pmufw

hello_te0820

u-boot

zynqmp_fsbl

zynqmp_fsbl_flash

zynqmp_pmufw

hello_te0808