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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modules and mainboards:

  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2...ZU5*
    • Engine: CG, EG, EV*
    • Speed: -1LI, -2LE,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS
      • Data width: 32bit
      • Size: def. 2GB*
      • Speed:***
    • eMMC
      • Data width: 8Bit
      • size: def. 8GB *
    • QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 128MB *
    • HyperRAM/Flash (optional, default not assembled)
      • size:*
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Lattice LCMXO2
    • PLL SI5338
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  • Interface
    • 132 x HP PL I/Os (3 banks)
    • ETH
    • USB
    • 4 GTR (for USB3, Sata, PCIe, DP)
    • MIO for UART
    • MIO for SD
    • MIO for PJTAG
    • JTAG
    • Ctrl
  • Power
    • 3.3V-5V Main Input
    • 3.3V Controller Input
    • Variable Bank IO Power Input
  • Dimension
    • 4 cm x 5 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension


  • SoC/FPGA
    • Package: SFVC784 CLG484
    • Device: Xilinx Z-7020
    • Speed: -1 *
    • Temperature: C grade *.
  • Xilinx XC7Z020 SoC:
    • Processing system (PS):
      • ARM® CortexTM-A9 MPCoreTM with CoreSightTM.
      • L1 Cache: 32KB Instruction, 32KB Data per processor.
      • L2 Cache: 512KB.
    • Programmable logic (PL):
      • Artix-7 FPGA Equivalent.
      • Logic cells: 85K.
      • Look-Up Tables: 53200.
      • Block RAM: 4.9 Mb.
      • DSP slices: 220.
      • Peak DSP performance: 276 GMACs.
      • 2x 12 bit, 1 MSPS ADCs with up to 17 Differential Inputs.
    • 120 x PL HR I/O (48 differential pairs and 24 single-ended).
    • 2x PS MIOs (shared with UART TX/RX ZYNQ-FTDI).
  • 1GByte DDR3L SDRAM memory (2 x [256Mbit x 16]), 32-bit wide data bus.
  • 32MByte Quad SPI Flash memory.
  • RAM/Storage
    • Low Power DDR3 SDRAM on PS
      • Data width: 32bit
      • Size: def. 1GB *
      • Speed: 1600 Mbps **
    • QSPI boot Flash
      • Data width: 4bit
      • size: 32MB *
    • MAC address serial EEPROM with EUI-
    48TM
    • 48™ node identity (Microchip 24AA025E48).
    • 512Kb
    Serial EEPROM memory (CAT24C512).
    • user MAC address serial EEPROM.
  • On Board
    • 10x 12-Bit Low Power SAR ADCs up to 2 MSPS (NCD98011).
    • Low Power Oscillators.
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512).
    Highly integrated full-featured hi-speed USB 2.0 ULPI transceiver
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C
    -EZK
    • ).
    • Single
    chip
    • chip High Speed USB
    Interface 2
    • 2.0
    High Speed 480Mbs
    • to UART/JTAG Interface (Xilinx License included) (FTDI FT2232H
    -56Q
    • )
    , including microUSB-B connector
    • .
    • 2xUser RGB LEDs (Green), LED FPGA DONE (Green).
    • 2 x Tactile Switches (User), 1 x Tactile Switche (Reset).
  • Interface
    • 120 x HR PL I/Os (3 banks).
    • 2x PS MIOs (shared with UART TX/RX ZYNQ-FTDI).
    • 1 Gbps RGMII Ethernet interface.
    2 x Tactile Switches (User), 1 x Tactile Switche (Reset)
    • High Speed USB2 ULPI with full OTG support.
    • High Speed USB 2.0 to UART/JTAG Interface, including microUSB-B connector.
    • Card Connector microSD™.
    • JTAG.
  • Power
    • On-board high-efficiency DC-DC converters for all voltages used.
  • DimensionBoard Size:
      • 65 x 45 mm
      .
    • Notes
      • * depends on assembly version
      • ** depends on used Zynq and DDR3 combination



    Block Diagram

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    add drawIO object here.

    Note

    For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


    ...

    Scroll Title
    anchorTable_SIP_JTG
    titleJTAG pins connection

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    JTAG Signal

    B2B Connector

    		Notes
    TMSJP2-7Also Connected to U39 (FTDI)
    TDIJP2-11Also Connected to U39 (FTDI)
    TDOJP2-10Also Connected to U39 (FTDI)
    TCK

    JP2-8

    		Also Connected to U39 (FTDI)


    MIO Pins

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    you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

    Example:

    MIO PinConnected toB2BNotes
    MIO12...14

    SPI_CS , SPI_DQ0... SPI_DQ3

    SPI_SCK

    		J2QSPI


    ...