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anchor	Figure_OV_MC
title	TExxxx main components

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draw.io Diagram

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Xilinx Zynq XC7Z SoC, U5 (Top)
4Gbit DDR3/L SDRAM, U13 (Top)
4Gbit DDR3/L SDRAM, U12 (Top)
32MByte Quad SPI Flash memory, U7 (Top)
2Kbit MAC address serial EEPROM with EUI-48TM node identity, U24 (Top)
512Kb Serial EEPROM memory, U21 (Top)
10x 12-Bit Low Power SAR ADCs, U1..U4, U10, U11, U15..U17, U19 (Top)
High-speed USB 2.0 ULPI transceiver, U18 (Top)
Single chip USB Interface 2.0 to UART / JTAG, U39 (Top)
MicroUSB-B connector, J13 (Top).

Initial Delivery State

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hidden	true
id	Comments

Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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