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Scroll Title
anchorTable_SIP_B2B
titleGeneral PS-PL I/O to B2B connectors information

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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
MIO 500JP123.3V-
HR 35JP1483.3V-
HR 13JP2503.3V-
HR 33JP2223.3V-


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Scroll Title
anchorTable_SIP_TPs
titleTest Points Information

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Test PointSignalConnected toNotes
TP1+1.0V

U37, DC-DC Converter

PL-VCCINT
TP2ADC_VAAU37, LDO Regulator
ADC_VAA Analog supply/reference, (3.3V)
TP3+1.5VU43, DC-DC Converter-
TP4+1.8VU45, DC-DC Converter-
TP5VTT-U47,3A Sink/Source DDR Termination Regulator (VTT/VTTREF, 0.75V), U47 (Bottom)3A Sink/Source DDR Termination Regulator (0.75V)
TP6VTTREF
-
TP7+5.0V
-
TP8+3.3V
-
TP9+5.0V_VAA
-
TP10+3.3V_ADC
-
TP11GND
-
TP12GND
-
TP13SPI-DQ3/M0

TP14GND


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