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@Guillermo: Hier die JP2 Stecker Pins  wo PWN rausgeführt wird 

Micro USB -JTAG/UART

@Guillermo: Hier kurz  erklären das UART JTAG über FTDI möglich ist und Hinweis das JTAG auch auf B2B J2 geht und nur einer JTAG bedienen darf

Micro SD Socket

A microSD™ card connector (J2) is connected via U35 (SD/SDIO Multiplexer - Level Translator) to Zynq PS (Bank501/SDIO 0). It is a Push-On/Push-Off socket type, and work with a voltage level of 3.3V.

MIO Pins

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hiddentrue
idComments

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

A microUSB-B connector (J13) is connected to the FTDI. It provides the ability to communicate to the PL FPGA via JTAG, as well as to the PS UART (UART 0).

Caution: because the TE0716 also provides UART and JTAG access to the FPGA through B2B connectors JP1 and JP2 respectively, ONLY ONE connection for UART, and ONLY ONE connection for JTAG, should be used at the time! (please read "UART Interface" and "JTAG Interface" above in the "Board to Board (B2B)" Section).

Micro SD Socket

A microSD™ card connector (J2) is connected via U35 (SD/SDIO Multiplexer - Level Translator) to Zynq PS (Bank501/SDIO 0). It is a Push-On/Push-Off socket type, and work with a voltage level of 3.3V.

MIO Pins

Page properties
hiddentrue
idComments

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

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SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

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PS MIO banks 500/501 signal connections to interface.

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MIO PinConnected toB2BNotes
1
MIO12...
6
14

SPI

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_CS , SPI

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_DQ0... SPI

-

_DQ3

SPI

-

_SCK

J2QSPI


PS MIO banks 500/501 signal connections to interface.

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MIO PinConnected toB2BNotes
1..6

SPI-CS , SPI-DQ0... SPI-DQ3

SPI-SCK

-QSPI Flash-QSPI Flash, U7
11..13LED1_R..G..B-LED D4
14, 15UART_RX_ZYNQ, UART_TX_ZYNQJP13.3V Voltage level. Also Connected to U36-2. To use this signal from B2B connector, "UART_OB_DISABLE" (JP1-11) must be "High".
16..27ETH-TXCK, ETH-TXD0..ETH-TXD3, ETH-TXCTL, ETH-RXCK, ETH-RXD0..ETH-RXD3, ETH-RXCTL-Gigabit ETH Transceiver, U8
28..39OTG-DATA0..OTG-DATA7, OTG-DIR, OTG-STP, OTG-NXT, OTG-CLK-USB 2.0 ULPI transceiver, U18
40..45PS_SD_CLK, PS_SD_CMD, PS_SD_DAT0..PS_SD_DAT3J23.3V Voltage level. Connected to PS via U35 (SD/SDIO Multiplexer - Level Translator)
46, 47I2C_SCL, I2C_SDA-General Purpose EEPROM, U21
MAC EEPROM, U24
51PHY-RST-Gigabit ETH Transceiver, U8
USB 2.0 ULPI transceiver, U18
52, 53ETH-MDC, ETH-MDIO-Gigabit ETH Transceiver, U8


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There is also a 4Kbit configuration EEPROM U40 (M93C66) wired to the FT2232H chip via Microwire bus which holds pre-programmed license code to support Xilinx programming tools. Refer to the FTDI datasheet to get information about the capacity of the FT2232H chip.

ATTENTION!: Do not access the FT2232H EEPROM using FTDI programming tools. By doing it, you could erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license, the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

Channel A of the FTDI chip is configured as JTAG interface connected to the BANK 0 Zynq SoC.

Channel B can be used as UART interface routed to the 2-Bit Bus Switch, which routes to the BANK 500 Zynq SoC, when the Output of the Bus Switch is Enable, and is available for other user-specific purposes.

  • Part number: USB3320C-EZK
  • Supply voltage: 1.8V and 3.3V.
  • Reference clock: 52.00MHz
  • Temperature: Industrial Range -40°C to +85°C.

erasing user EEPROM content.

Channel A of the FTDI chip is configured as JTAG interface connected to the BANK 0 Zynq SoC.

Channel B can be used as UART interface through the 2-Bit Bus Switch (U36), which routes to the BANK 500 Zynq SoC, when the Output of the Bus Switch is Enable, and is available for other user-specific purposes. Caution: UART is also routed to the B2B JP1 connector, but ONLY ONE connection for UART should be used at the time!.

  • Part number: FT2232H-56Q
  • Supply voltage: 3.3V (3.0V - 3.6V).
  • Reference clock: 12.00MHz
  • Temperature: Industrial Range -40°C to +85°C.
Note
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U39 Pin Signal NameConnected toSignal DescriptionNote
DPD_JTAG_PJ13-2USB Data Signal Plus3.3V Voltage level
DMD_JTAG_NJ13-3USB Data Signal Minus3.3V Voltage level
ADBUS0TCKJP2-8,
TCK_0 (FPGA PL BANK 0)		Clock Signal Output3.3V Voltage level.
MPSSE Mode
ADBUS1TDIJP2-11,
TDI_0 (FPGA PL BANK 0)		Serial Data Output3.3V Voltage level.
MPSSE Mode
ADBUS2TDOJP2-10,
TDO_0 (FPGA PL BANK 0)		Serial Data Input3.3V Voltage level.
MPSSE Mode
ADBUS3TMSJP2-7,
TMS_0 (FPGA PL BANK 0)		Output Signal Select3.3V Voltage level.
MPSSE Mode
BDBUS0UART_TX_OBU36-5Asynchronous serial TXDU36-3 Bus Switch pin connects later this signal to UART_RX_ZYNQ when UART_OB_DISABLE is low or floating.
BDBUS1UART_RX_OBU36-6Asynchronous serial RXDU36-2 Bus Switch pin connects later this signal to UART_TX_ZYNQ when UART_OB_DISABLE is low or floating.
OSCIOSCI
Oscillator input-
EECS, EECLK, EEDATAEECS, EECLK, EEDATAU40-1..3EEPROM interface-
-UART_OB_DISABLEJP1-11Enable signal of the FTDI-PS_UART Bus Switch U36.Active Low!.
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U?? Pin Signal NameConnected toSignal Description


LEDs

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DesignatorColorConnected toActive LevelNote
D3GreenDONE (FPGA BANK 0)

Low

When LED is OFF, the FPGA is programmed.
D4RGBMIO11 (LED1_R)
MIO12 (LED1_G)
MIO13 (LED1_B)		High-
D5RGB

B34_L22_P (LED2_R)
B34_L22_N (LED2_G)
B34_L23_N (LED2_B)

High-


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