XPS_FX2 is a communication core to interface Xilinx Microblaze soft processor and a popular USB High Speed microcontroller Cypress CY7C68013A (also known as EzUSB FX2).
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(1) Address FIFO was designed to avoid FIFO draining before the EP ADDRESS changing. Will be fixed in further releases. (2) Set to 1 only if the user experience 8-bit data shifting after a received packet of data. Normally set to 0. |
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The point to point unidirectional buses use simple handshaking protocol.
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XPS_FX2 has a full access of a microprocessor to the core functionality through a 5 user 32-bit and 7 IPIF Interrupt registers attached to PLBv4.6 bus.
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The First (LSB) interrupt from user_logic is masked on the left!! |
The parts of the registers (or the whole registers) with a non-capital designation (e.g. wr_fifo_rst) are usually the names of the HDL signals connected to the described register.
The Control Register is used to control basic peripheral functions. All the bit flags are assembled here.
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(1) Endpoint EP8 is read only and is switched automatically when data arrives. To achieve maximal throughput use only one endpoint and prevent TX FIFO draining (TX FIFO empty should not occur). (2) Packet end timeout timer automatically asserts USB_PKTEND signal when TX_FIFO is empty for a programmed number of cycles and current USB EndPoint FIFO is not empty. Cycle timer is also reset when switched to EP8 – incoming data. The USB_PKTEND send current packet and enables the PC to receive packet smaller than 512 bytes. If user setup the timer properly then the packets are automatically send when there is no more data available in the TX_FIFO. |
This register is used to setup thresholds for interrupt triggering when FIFO occupancy reaches set number of words. For RX FIFO the prog_full flag goes high when number of words in a FIFO is higher than threshold. For TX FIFO the prog_empty flag goes high when number of words in a FIFO is lower than threshold.
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In the status register the peripheral reports of the current status. The tx_fifo_count can have 9-13 bits according to size of the TX_FIFO. This register is usually accessed using 16-bit reads
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Single beat write to this register puts a single word (4 bytes) to TX FIFO. For proper operation PLB clock frequency should be less or equal to TX_FIFO_Clk.
Single beat read from this register pops one word (4 bytes) from RX FIFO. For proper operation PLB clock frequency should be less or equal to RX_FIFO_Clk.
With INTR_IPIER register the user can enable/disable peripheral interrupt sources. With INTR_IPISR the user can identify interrupt source. Writing a value to INTR_IPISR also clears interrupt.
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By setting control register (CR) make sure that user not override the previously set bits. |
Resetting the TX_FIFO:
1. Write 0x00000001 to CR
2. Write 0x00000000 to CR
Resetting the RX_FIFO:
1. Write 0x00000002 to CR
2. Write 0x00000000 to CR
Setting the endpoint address to EP4
1. Write 0x00000010 to CR
XPS_NPI_DMA and XPS_FX2 custom IP blocks are both necessary to connect (throgh USB connection) host computer's software and TE USB FX2 module's DRAM.
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