To determine PCB revision and assembly variant from FPGA, TE0630 have dedicated user signals, which can be read by user core.
Board revision coded in 4 bits BR[3:0]
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Signal name | FPGA pin |
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BR0 | R19 | BR1 | V19 | BR2 | V20 | BR3 | T17 |
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To define low (zero) level BR pin connected to ground rail, to define high (one) level BR pin left float (open). These pins should be configured with "pullup" option in user design.
See Table 12 the table above for current list of board revisions.
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BR3 | BR2 | BR1 | BR0 | |
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0 | 0 | 0 | 0 | 00 Initial revision |
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Module assembly variant encoded using AV[3:0] pins.
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| title | Assembly variants pins |
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Signal name | FPGA pin |
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AV0 | Y20 | AV1 | R15 | AV2 | R16 | AV3 | R17 |
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Table 14: Assembly variants pins
To define low (zero) level AV pin connected to ground rail through zero resistor, to define high (one) level AV pin left float (open). These pins should be configured with "pullup" option in user design.
Available module assembly variants listed in Table 15the table below.
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| title | Module assembly variants |
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AV3 | AV2 | AV1 | AV0 | |
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0 | 0 | 0 | 0 | Base assembly variant |
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