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Template Revision 3.1

Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"

Change List 3.0 to


DateVersionChangesAuthor
2021-05-043.1.6
  • removed zynq_ from zynq_fsbl
ma
2021-04-283.1
  • Fix problem with pdf export and side scroll bar
  • update 19.2 to 20.2
  • add prebuilt content option
  • Change List 2.9 to 3.0
    • add fix table of content
    • add table size as macro
    • removed page initial creator
  • Custom_table_size_100
    Page properties
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    Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

    Figure template (note: inner scroll ignore/only only with drawIO object):

    Scroll Title
    anchorFigure_xyz
    titleText
    Scroll Ignore

    Create DrawIO object here: Attention if you copy from other page, use

    Scroll Only

    image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

  • Table template:

    • Layout macro can be use for landscape of large tables
    • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
  • Scroll Title
    anchorTable_xyz
    titleText
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueExampleComment12
  • ...
  • Overview
    .5
    • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
    • minor typos, formatting
    ma
    2021-04-273.1.4
    • Version History
      • changed from list to table
    • Design flow
      • removed step 5 from Design flow
      • changed link from TE Board Part Files to Vivado Board Part Flow
      • changed cmd shell from picture to codeblock
      • added hidden template for "Copy PetaLinux build image files", depending from hardware
      • added hidden template for "Power on PCB", depending from hardware
    • Usage update of boot process
    • Requirements - Hardware
      • added "*used as reference" for hardware requirements
    • all
      • placed a horizontal separation line under each chapter heading
      • changed title-alignment for tables from left to center
    • all tables
      • added "<project folder>\board_files" in Vivado design sources
    ma

    3.1.3
    • Design Flow
      • formatting
    • Launch
      • formatting
    ma

    3.1.2
    • minor typing corrections
    • replaced SDK by Vitis
    • changed from / to \ for windows paths
    • replaced <design name> by <project folder>
    • added "" for path names
    • added boot.src description
    • added USB for programming
    ma

    3.1.1
    • swapped order from prebuilt files
    • minor typing corrections
    • removed Win OS path length from Design flow, added as caution in Design flow
    ma

    3.1
    • Fix problem with pdf export and side scroll bar
    • update 19.2 to 20.2
    • add prebuilt content option


    3.0
    • add fix table of content
    • add table size as macro
    • removed page initial creator


    Custom_table_size_100

    Page properties
    hiddentrue
    idComments

    Notes :

    Linux with basic periphery of TE0808 Starterkit (TEBF0808 Carrier).

    Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

    Key Features

    Page properties
    hiddentrue
    idComments

    Notes :

    • Add basic key futures, which can be tested with the design
    Excerpt
    • Vitis/Vivado 2020.2
    • TEBF0808
    • Linux
    • USB
    • ETH
    • MAC from EEPROM
    • PCIe
    • SATA
    • SD
    • I2C
    • RGPIO
    • DP
    • user LED access
    • Modified FSBL for Si5338 programming / petalinux patch
    • Special FSBL for QSPI Programming

    Revision History

    Page properties
    hiddentrue
    idComments

    Notes :

    • add every update file on the download
    • add design changes on description
    DRHDesign Revision History2018

    Important General Note:

    • Export PDF to download, if vivado revision is changed!

    • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

      • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
        • Figure template (note: inner scroll ignore/only only with drawIO object):

          Scroll Title
          anchorFigure_xyz
          titleText


          Scroll Ignore

          Create DrawIO object here: Attention if you copy from other page, use


          Scroll Only

          image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



        • Table template:

          • Layout macro can be use for landscape of large tables
          • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)

        • Scroll Title
          anchorTable_
        • xyz
          title
        • Text

          Scroll Table Layout
          orientationportrait
          sortDirectionASC
          repeatTableHeadersdefault
          style
          widths
          sortByColumn1
          sortEnabledfalse
          cellHighlightingtrue

    Date
        • Example
    VivadoProject BuiltAuthorsDescription
    2021-05-122020.2TE0808-StarterKit-vivado_2020.2-build_5_20210512133800.zip
    TE0808-StarterKit_noprebuilt-vivado_2020.2-build_5_20210512133822.zip
    John Hartfiel
    • update board files
    • boot.scr update to vesion1 → image.ub on sd, emmc, USB possible
    2021-02-052020.2TE0808-StarterKit-vivado_2020.2-build_1_20210205120058.zip
    TE0808-StarterKit_noprebuilt-vivado_2020.2-build_1_20210205120122.zip
    John Hartfiel
    • bugfix ini.sh script usage
    2021-02-052020.2TE0808-StarterKit_noprebuilt-vivado_2020.2-build_1_20210204142828.zip
    TE0808-StarterKit-vivado_2020.2-build_1_20210204142713.zip
    John Hartfiel
    • 2020.2 update
    • add boot.scr file
    • device tree has change
    • petalinuxx fsbl patch (betaversion)
    2020-09-292019.2TE0808-StarterKit_noprebuilt-vivado_2019.2-build_15_20200928195324.zip
    TE0808-StarterKit-vivado_2019.2-build_15_20200928195304.zip
    John Hartfiel
    • bufix 8GB board part files
    2020-09-222019.2TE0808-StarterKit_noprebuilt-vivado_2019.2-build_14_20200922071643.zip
    TE0808-StarterKit-vivado_2019.2-build_14_20200922071704.zip
    John Hartfiel
    • new assembly variants
    2020-03-252019.2TE0808-StarterKit_noprebuilt-vivado_2019.2-build_8_20200325083508.zip
    TE0808-StarterKit-vivado_2019.2-build_8_20200325083436.zip
    John Hartfiel
    • script update
    2020-01-222019.2TE0808-StarterKit_noprebuilt-vivado_2019.2-build_3_20200122142340.zip
    TE0808-StarterKit-vivado_2019.2-build_3_20200122142318.zip
    John Hartfiel
    • 2019.2 update
    • Vitis support
    • FSBL SI programming procedure update 
    • petalinux device tree and u-boot update
    2019-08-092018.3TE0808-StarterKit_noprebuilt-vivado_2018.3-build_07_20190809131638.zip
    TE0808-StarterKit-vivado_2018.3-build_07_20190809131620.zip
    John Hartfiel
    • new assembly variants
    • small fsbl update(supports all GTR disabled now)
    2019-05-072018.3TE0808-StarterKit_noprebuilt-vivado_2018.3-build_05_20190507124429.zip
    TE0808-StarterKit-vivado_2018.3-build_05_20190507124418.zip
    John Hartfiel
    • new assembly variant
    • TE Script update
    • rework of the FSBLs
    • some additional Linux features
    • MAC from EEPROM
    • new assembly variants
    • remove special compiler flags, which was needed in 2018.2
    2018-07-11
    Comment
    12



  • ...
  • Overview

    Scroll Ignore
    scroll-pdftrue
    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue


    Page properties
    hiddentrue
    idComments

    Notes :

    Linux with basic periphery of TE0808 StarterKit (TEBF0808 Carrier).

    Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

    Key Features

    Page properties
    hiddentrue
    idComments

    Notes :

    • Add basic key futures, which can be tested with the design


    Excerpt
    • Vitis/Vivado 2020.2
    • TEBF0808
    • Linux
    • USB
    • ETH
    • MAC from EEPROM
    • PCIe
    • SATA
    • SD
    • I2C
    • RGPIO
    • Display Port (DP)
    • user LED access
    • Modified FSBL for Si5338 programming / petalinux patch
    • Special FSBL for QSPI Programming

    Revision History

    Page properties
    hiddentrue
    idComments

    Notes :

    • add every update file on the download
    • add design changes on description


    Scroll Title
    anchorTable_DRH
    title-alignmentcenter
    titleDesign Revision History

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Requirements

    Software

    Page properties
    hiddentrue
    idComments

    Notes :

    • list of software which was used to generate the design
    Scroll Title
    anchorTable_SW
    titleSoftware
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueSoftwareVersionNoteVitis2020.2needed, Vivado is included into Vitis installationPetaLinux2020.2neededSI ClockBuilder Pro---optional

    Hardware

    Page properties
    hiddentrue
    idComments

    Notes :

    • list of software which was used to generate the design

    Basic description of TE Board Part Files is available on TE Board Part Files.

    Complete List is available on <design name>/board_files/*_board_files.csv

    Design supports following modules:

    Scroll Title
    anchorTable_HWM
    titleHardware Modules
    Scroll Table Layout
    20180220180711091558201802201807110910492017.42017410201805240912312017410201805240912082017.4201740720180329145308201740720180329145246 variant20180206201742017405201802060827402017405201802060827222017.42017405201802050832312017405201802050832082017.4201740520180117094213_noprebuilt201740520180117094231solved USB problem board part update2017.4201740320180115092306_noprebuilt2017403201801150925112017
    DateVivadoProject BuiltAuthorsDescription
    2021-05-122020.2TE0808-StarterKit-vivado_2020.2-build_5_20210512133800.zip
    TE0808-StarterKit_noprebuilt-vivado_2020.2-build_5_20210512133822.zip
    John Hartfiel
    • update board files
    • boot.scr update to version1 → image.ub on sd, eMMC, USB possible
    2021-02-052020.2TE0808-StarterKit-vivado_2020.2-build_1_20210205120058.zip
    TE0808-StarterKit_noprebuilt-vivado_2020.2-build_1_20210205120122.zip
    John Hartfiel
    • bugfix init.sh script usage
    2021-02-052020.2TE0808-StarterKit_noprebuilt-vivado_2020.2-build_1_20210204142828.zip
    TE0808-StarterKit-vivado_
    2020.2-build_1_20210204142713.zipJohn Hartfiel
    • small petalinux changes
    • IO renaming
    • PL Design changes
    • additional notes for FSBL generated with Win SDK
    • changed *.bif
    2018-05-24
    • 2020.2 update
    • add boot.scr file
    • device tree has change
    • petalinux fsbl patch (betaversion)
    2020-09-292019.2TE0808-StarterKit_noprebuilt-vivado_2019.2-build_15_20200928195324.zip
    TE0808-StarterKit-vivado_
    2019.2-build_15_20200928195304.zipJohn Hartfiel
    • solved Linux flash issue
    2018-03-29
    • bugfix 8GB board part files
    2020-09-222019.2TE0808-StarterKit_noprebuilt-vivado_2019.2-build_14_20200922071643.zip
    TE0808-StarterKit-vivado_
    2019.2-build_14_20200922071704.zipJohn Hartfiel
    • new assembly
    • variants
    2020-03-252019.2TE0808-StarterKit_noprebuilt-vivado_2019.2-build_8_20200325083508.zip
    TE0808-StarterKit-vivado_
    2019.2-build_8_20200325083436.zipJohn Hartfiel
    • same clk for both VIO
    2018-02-05
    • script update
    2020-01-222019.2TE0808-StarterKit_noprebuilt-vivado_2019.2-build_3_20200122142340.zip
    TE0808-StarterKit-vivado_
    2019.2-build_3_20200122142318.zipJohn Hartfiel
    • solved  JTAG/Linux problem
    2018-01-17
    • 2019.2 update
    • Vitis support
    • FSBL SI programming procedure update 
    • petalinux device tree and u-boot update
    2019-08-092018.3TE0808-StarterKit_noprebuilt-vivado_2018.3-build_07_20190809131638.zip
    TE0808-StarterKit
    -vivado_2018.3-build_07_20190809131620.zipJohn Hartfiel
    • new assembly variants
    • small
    2018-01-15
    • fsbl update(supports all GTR disabled now)
    2019-05-072018.3TE0808-StarterKit_noprebuilt-vivado_2018.3-build_05_20190507124429.zip
    TE0808-StarterKit
    -vivado_2018.3-build_05_20190507124418.zipJohn Hartfiel
    • rework board part files
    • rework design
    2017-12-18
    • new assembly variant
    • TE Script update
    • rework of the FSBLs
    • some additional Linux features
    • MAC from EEPROM
    • new assembly variants
    • remove special compiler flags, which was needed in 2018.2
    2018-07-112018.2TE0808-StarterKit_noprebuilt-vivado_20172018.2-build_0702_2017121915174920180711091558.zip
    TE0808-StarterKit-vivado_20172018.2-build_0702_2017121915172820180711091049.zip
    John Hartfiel
    • initial release

    Release Notes and Know Issues

    Page properties
    hiddentrue
    idComments
    Notes :
    • add known Design issues and general notes for the current revision
    • do not delete known issue, add fixed version time stamp if  issue fixed
    Scroll Title
    anchorTable_KI
    titleKnown Issues
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueIssuesDescriptionWorkaround/SolutionTo be fixed versionFlash access on LinuxDevice tree is not correct on Linuxadd compatibility to "compatible “jedec,spi-nor”"Solved with 20180524 updateUSB UART Terminal is blocked / SDK Debugging is blockedThis happens only with 2017.4 Linux , when JTAG connection is established on Vivado HW Manager.

    Do not use HW Manager connection, or if debugging is nessecary:

    1. Boot linux with usb terminal
    2. From the terminal: root root mount ifconfig eth0
    3. Open two new SSH terminals via ethernet: root root , run user application ...
    4. Exit and close the usb terminal
    Solved with 20180205 update
    • small petalinux changes
    • IO renaming
    • PL Design changes
    • additional notes for FSBL generated with Win SDK
    • changed *.bif
    2018-05-242017.4TE0808-StarterKit_noprebuilt-vivado_2017.4-build_10_20180524091231.zip
    TE0808-StarterKit-vivado_2017.4-build_10_20180524091208.zip
    John Hartfiel
    • solved Linux flash issue
    2018-03-292017.4TE0808-StarterKit_noprebuilt-vivado_2017.4-build_07_20180329145308.zip
    TE0808-StarterKit-vivado_2017.4-build_07_20180329145246.zip
    John Hartfiel
    • new assembly variant
    2018-02-062017.4TE0808-StarterKit_noprebuilt-vivado_2017.4-build_05_20180206082740.zip
    TE0808-StarterKit-vivado_2017.4-build_05_20180206082722.zip
    John Hartfiel
    • same clk for both VIO
    2018-02-052017.4TE0808-StarterKit_noprebuilt-vivado_2017.4-build_05_20180205083231.zip
    TE0808-StarterKit-vivado_2017.4-build_05_20180205083208.zip
    John Hartfiel
    • solved  JTAG/Linux problem
    2018-01-172017.4TE0808-StarterKit-vivado_2017.4-build_05_20180117094213.zip
    TE0808-StarterKit_noprebuilt-vivado_2017.4-build_05_20180117094231.zip
    John Hartfiel
    • solved USB problem
    • small board part update
    2018-01-152017.4

    TE0808-StarterKit-vivado_2017.4-build_03_20180115092306.zip
    TE0808-StarterKit_noprebuilt-vivado_2017.4-build_03_20180115092511.zip

    John Hartfiel
    • rework board part files
    • rework design
    2017-12-182017.2TE0808-StarterKit_noprebuilt-vivado_2017.2-build_07_20171219151749.zip
    TE0808-StarterKit-vivado_2017.2-build_07_20171219151728.zip
    John Hartfiel
    • initial release


    Release Notes and Know Issues

    Page properties
    hiddentrue
    idComments
    Notes :
    • add known Design issues and general notes for the current revision
    • do not delete known issue, add fixed version time stamp if issue fixed

    Scroll Title
    anchorTable_KI
    title-alignmentcenter
    titleKnown Issues

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    IssuesDescriptionWorkaround/SolutionTo be fixed version
    Flash access on LinuxDevice tree is not correct on Linuxadd compatibility to "compatible “jedec,spi-nor”"Solved with 20180524 update
    USB UART Terminal is blocked/ SDK Debugging is blockedThis happens only with 2017.4 Linux, when JTAG connection is established on Vivado HW Manager.

    Do not use HW Manager connection, or if debugging is necessary:

    1. Boot linux with usb terminal
    2. From the terminal: root root mount ifconfig eth0
    3. Open two new SSH terminals via ethernet: root root , run user application ...
    4. Exit and close the usb terminal
    Solved with 20180205 update


    Requirements

    Software

    Page properties
    hiddentrue
    idComments

    Notes :

    • list of software which was used to generate the design


    4GB      
    Scroll Title
    anchorTable_SW
    title-alignmentcenter
    titleSoftware

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
    TE0808-ES1          es1_2gb      REV03|REV02 2GB      64MB       NA         NA               Not longer supported by vivado       
    TE0808-ES2          es2_2gb      REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado                   
    TE0808-2ES2         2es2_2gb     REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado                
    TE0808-04-09EG-1EA  9eg_1e_2gb   REV04       2GB      64MB       NA         NA               NA                                     
    TE0808-04-09EG-1EB  9eg_1e_4gb   REV04       4GB      64MB       NA         NA               NA                                     
    TE0808-04-09EG-1ED  9eg_1e_4gb   REV04       4GB      64MB       NA         1 mm connectorsNA                                     
    TE0808-04-09EG-2IB  9eg_2i_4gb   REV04       4GB      64MB       NA         NA               NA                                     
    TE0808-04-15EG-1EB  15eg_1e_4gb  REV04       
    SoftwareVersionNote
    Vitis2020.2needed, Vivado is included into Vitis installation
    PetaLinux2020.2needed
    SI ClockBuilder Pro---optional


    Hardware

    Page properties
    hiddentrue
    idComments

    Notes :

    • list of hardware which was used to generate the design
    • mark the module and carrier board, which was used tested with an *

    Basic description of TE Board Part Files is available on TE Board Part Files.

    Complete List is available on "<project folder>\board_files\*_board_files.csv"

    Design supports following modules:


    Scroll Title
    anchorTable_HWM
    title-alignmentcenter
    titleHardware Modules

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
    TE0808-ES1          es1_2gb      REV03|REV02 2GB      64MB       NA         NA               Not longer supported by vivado       
    TE0808-ES2          es2_2gb      REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado                   
    TE0808-2ES2         2es2_2gb     REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado                
    TE0808-04-09EG-1EA  9eg_1e_2gb   REV04       2GB      64MB       NA         NA               NA                                     
    TE0808-04-09EG-1EE  1EB  9eg_1e_4gb   REV04       4GB      128MB      64MB       NA         NA               NA                                     
    TE0808-04-09EG-1EL  1ED  9eg_1e_4gb   REV04       4GB      128MB      64MB       NA         1 mm connectorsNA                                     
    TE0808-04-09EG-2IB  9eg_2i_4gb   REV04       4GB      64MB       NA         NA               NA                                     
    TE0808-04-15EG-1EB  15eg_1e_4gb  REV04       4GB      64MB       NA         NA               NA                                     
    TE0808-04-09EG-1EE  9eg_1e_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-09EG-1EL  9eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-04-09EG-2IE  9eg_2i_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-15EG-1EE  15eg_1e_4gb  REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-06EG-1EE  6eg_1e_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-06EG-1E3  6eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-04-6GI21-L   6eg_2i_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-04-6BI21-A   6eg_1i_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-9GI21-A   9eg_2i_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-9BE21-A   9eg_1e_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-6BE21-L   6eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-04-6BE21-A   6eg_1e_4gb   REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-9BE21-L   9eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-04-BBE21-A   15eg_1e_4gb  REV04       4GB      128MB      NA         NA               NA                                     
    TE0808-04-6BI21-X   6eg_1i_4gb   REV04       4GB      128MB      NA         NA               U41 replaced with schottky diodes    
    TE0808-05-6BE21-L   6eg_1e_4gb   REV05       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-05-6BE21-A   6eg_1e_4gb   REV05       4GB      128MB      NA         NA               NA                                     
    TE0808-05-6BI21-D   6eg_1i_4gb   REV05       4GB      128MB      NA         1 mm connectorsSoC without encryption               
    TE0808-05-6BI21-X   6eg_1i_4gb   REV05       4GB      128MB      NA         NA               U41 replaced with schottky diodes    
    TE0808-05-6BI41-X   6eg_1i_8gb   REV05       8GB      128MB      NA         NA               U41 replaced with schottky diodes    
    TE0808-05-9BE21-A   9eg_1e_4gb   REV05       4GB      128MB      NA         NA               NA                                     
    TE0808-05-9BE21-L   9eg_1e_4gb   REV05       4GB      128MB      NA         1 mm connectorsNA                                     
    TE0808-05-9BI41-X   9eg_1i_8gb   REV05       8GB      128MB      NA         NA               U41 replaced with schottky diodes    
    TE0808-05-9GI21-A   9eg_2i_4gb   REV05       4GB      128MB      NA         NA               NA                                     
    TE0808-05-9GI21-C   9eg_2i_4gb   REV05       4GB      128MB      NA         NA               SoC without encryption               
    TE0808-05-BBE21-A   15eg_1e_4gb  REV05       4GB      128MB      NA         NA               NA                                     
    TE0808-05-BBE21-L   15eg_1e_4gb  REV05       4GB      128MB      NA         1 mm connectorsNA    


    Note: Design contains also Board Part Files for TE0808 only configuration, this boart board part files are not used for this reference design.

    Design supports following carriers:

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    Carrier ModelNotes
    TEBF0808Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended


    Additional HW Requirements:

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    Additional HardwareNotes
    DP Display Port Monitor

    Optional HW
    Not all monitors are supported, also Adapter to other  other Standard can make droubletrouble.
    Design was testet with  tested with DELL U2412M

    USB KeyboardOptional HW
    Can be used to get access to console which is show on DPDisplay Port
    USB StickOptional HW
    USB was tested with USB memory stick
    Sata SATA DiskOptional HW
    PCIe CardOptional HW
    ETH cableOptional HW
    Ethernet works with DHCP, but can be setup also manually
    SD cardwith fat32 partition


    Content

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    Notes :

    • content of the zip file

    For general structure and of the reference design, see Project Delivery - Xilinx devices

    Design Sources

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    TypeLocationNotes
    Vivado<design name>/<project folder>\block_design
    <design name>/<project folder>\constraints
    <design name>/<project folder>\ip_lib
    <project folder>\board_files
    Vivado Project will be generated by TE Scripts
    Vitis<design name>/<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
    PetaLinux<design name>/os/<project folder>\os\petalinuxPetaLinux template with current configuration



    Additional Sources

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    TypeLocationNotes
    SI5345<design name><project folder>/misc/Si5345SI5345 Project with current PLL Configuration
    init.sh<design name><project folder>/sd/Additional Initialization Script for Linux


    Prebuilt

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    Notes :

    • prebuilt files
    • Template Table:

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        titlePrebuilt files

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        File

        File-Extension

        Description

        BIF-File*.bifFile with description to generate Bin-File
        BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
        BIT-File*.bitFPGA (PL Part) Configuration File
        Boot Source*.scr

        Distro Boot file

        DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

        Debian SD-Image

        *.img

        Debian Image for SD-Card

        Diverse Reports---Report files in different formats
        Hardware-Platform-SpecificationDescription-FilesFile*.xsaExported Vivado Hardware Specification hardware description file for Vitis and PetaLinux
        LabTools Project-File*.lprVivado Labtools Project File

        MCS-File

        *.mcs

        Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

        MMI-File

        *.mmi

        File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

        OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
        Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

        SREC-File

        *.srec

        Converted Software Application for MicroBlaze Processor Systems





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    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
    BIT-File*.bitFPGA (PL Part) Configuration File
    Boot Source*.scr

    Distro Boot file

    DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
    Diverse Reports---Report files in different formats
    Hardware-Platform-SpecificationDescription-FilesFile*.xsaExported Vivado Hardware Specification hardware description file for Vitis and PetaLinux
    LabTools Project-File*.lprVivado Labtools Project File
    OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
    Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


    Download

    Reference Design is only usable with the specified Vivado/SDKVitis/PetaLinux /SDx version. Do never use different Versions of Xilinx Software for the same Project.

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    Reference Design is available on:

    Design Flow

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    Notes :
    • Basic Design Steps

    • Add/ Remove project specific description


    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunchlaunch.

    Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

    TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK Vitis GUI.   For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

    Note

    Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

      Image Removed
    2. Press 0 and enter to start "Module Selection Guide"
    3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
    4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
      1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
        Note: Select correct one, see TE Board Part Files
                  Important: Use Board Part Files, which ends with *_tebf0808
    5. Create XSA and export to prebuilt folder
      1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
        Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
    6. Create Linux (bl31.elf, uboot.elf, image.ub, boot.src, bl31.elf) with exported XSA
      1. XSA is exported to "prebuilt\hardware\<short name>"
        Note: HW Export from Vivado GUI create another path as default workspace.
      2. Create Linux images on VM, see PetaLinux KICKstart
        1. Use TE Template from /os/petalinux
    7. Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
      1. prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
    8. Generate Programming Files with Vitis
      Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Scripts generate
      Code Block
      languagebash
      themeMidnight
      title_create_win_setup.cmd/_create_linux_setup.sh
      ------------------------Set design paths----------------------------
      -- Run Design with: _create_win_setup
      -- Use Design Path: <absolute project path>
      --------------------------------------------------------------------
      -------------------------TE Reference Design---------------------------
      --------------------------------------------------------------------
      -- (0)  Module selection guide, project creation...prebuilt export...
      -- (1)  Create minimum setup of CMD-Files and exit Batch
      -- (2)  Create maximum setup of CMD-Files and exit Batch
      -- (3)  (internal only) Dev
      -- (4)  (internal only) Prod
      -- (c)  Go to CMD-File Generation (Manual setup)
      -- (d)  Go to Documentation (Web Documentation)
      -- (g)  Install Board Files from Xilinx Board Store (beta)
      -- (a)  Start design with unsupported Vivado Version (beta)
      -- (x)  Exit Batch (nothing is done!)
      ----
      Select (ex.:'0' for module selection guide):


    9. Press 0 and enter to start "Module Selection Guide"
    10. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
      1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
        Note: Select correct one, see TE Board Part Files
                  Important: Use Board Part Files, which ends with *_tebf0808
    11. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

      Code Block
      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
      TE::hw_build_design -export_prebuilt


      Info

      Using Vivado GUI is the same, except file export to prebuilt folder.


    12. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
      • use TE Template from "<project folder>\os\petalinux"
      • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

      • The build images are located in the "<plnx-proj-root>/images/linux" directory

    13. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

    14. Copy PetaLinux build image files to prebuilt folder
      • copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

        Info

        "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"


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        This step depends on Xilinx Device/Hardware

        for Zynq-7000 series

        • copy u-boot.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

        for ZynqMP

        • copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

        for ...

        • ...


    15. Generate Programming Files with Vitis

      Code Block
      languagepy
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      titlerun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
      (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note: 
      TE::sw_run_vitis -all
      TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


      Note

      TCL scripts generate also platform project, this must be done

      manuelly

      manually in case GUI is used. See Vitis


    Launch

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    Note:

    • Programming and Startup procedure

    For basic board setup, LEDs... see: TEBF0808 Getting Started

    Programming

    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Xilinx documentation for programming and debugging: Vivado/SDKVitis/SDSoC-Xilinx Software Programming and Debugging

    Get prebuilt boot binaries

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
    2. Press 0 and enter to start "Module Selection Guide"
      1. Select assembly version
      2. Validate selection
      3. Select

        Create

        create and open delivery binary folder

        Info

        Note: Folder

        (

        "<project

        foler>/

        folder>\_binaries_

        <Artikel

        <Article Name>

        )

        " with subfolder

        (

        "boot_<app name>

        )

        " for different applications will be generated


    QSPI-Boot mode

    Optional

    Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

    1. Connect JTAG and power on carrier with module
    2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd

      "Type on Vivado TCL Console:

      "

      Code Block
      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
      TE::pr_program_flash -swapp u-boot

      Note:
      
      TE::pr_program_flash -swapp hello_te0808 (optional)


      Note

      To program with

      SDK

      Vitis/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

               optional "TE::pr_program_flash-swapp hello_te0803" possible


    3. Copy image.ub and boot.scr on SD-Card or USB
      • use files from
      (
      • "<project
      foler>/
      • folder>\_binaries_
      <Articel
      • <Article Name>
      )/ <design_name>/prebuilt/readme_
      • "<project folder>\prebuilt\file_location.txt"
    4. Set Boot Mode to QSPI-Boot and insered insert SD or USB.
      • Depends on Carrier, see carrier TRM.
      • TEBF0808 change automatically the Boot Mode to SD, if SD is
      insered
      • inserted, optional CPLD Firmware without Boot Mode changing for
      mircoSD
      • microSD Slot is available on the download area

    SD-Boot mode

    1. Copy image.ub, boot.src and Boot.bin on SD-Card
      • use files from ("<project foler>/folder>\_binaries_<Articel <Article Name>)/\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
      • or use prebuilt file location, see <design_name>/prebuilt/readme_"<project folder>\prebuilt\file_location.txt"
    2. Set Boot Mode to SD-Boot.
      • Depends on Carrier, see carrier TRM.
    3. Insert SD-Card in SD-Slot.

    JTAG

    Not used on this Example.

    Usage

    1. Prepare HW like described on section 54396545 Programming
    2. Connect UART USB (most cases same as JTAG XMOD)
    3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

      Info

      Note: See TRM of the Carrier, which is used.


      Tip

      Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
      The boot options described above describe the common boot processes for this hardware; other boot options are possible.
      For more information see Distro Boot with Boot.scr


    4. (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
    5. (Optional) Connect Sata SATA Disc
    6. (Optional) Connect DisplayPort Display Port Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
    7. (Optional) Connect Network Cable
    8. Power On PCB


      Note:

      Expand
      titleboot process

      1. ZynqMP Boot ROM loads

      PMU Firmware and 

      FSBL from SD/QSPI into OCM,

      2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF

      (bl31.elf)

      and U-boot from SD/QSPI into DDR,

      3. U-boot

      load

      loads Linux (image.ub) from SD/QSPI/... into DDR

      .


    Linux

    1. Open Serial Console (e.g. putty)
      • Speed: 115200
      • select COM Port

      :
      • Info

        Win OS, see device manager, Linux OS

      see 
      • see dmesg |grep

      tty 
      • tty (UART is *USB1)


    2. Linux Console:

      Code Block
      languagebash
      themeMidnight
      petalinux login: root
      Password: root


      Info

      Note: Wait until Linux boot finished

      For Linux Login use:
      User Name: root

    3. Password: root

    4. You can use Linux shell now.

      1. I2C 0 Bus type: i2cdetect -y -r 0
      2. ETH0 works with udhcpc
      3. USB type  "lsusb" or connect USB device
      4. PCIe type "lspci"
      Option


      Code Block
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      i2cdetect -y -r 0	(check I2C 1 Bus)
      udhcpc				(ETH0 check)
      lsusb				(USB check)
      lspci               (PCIe check)


    5. Option Features

      • Webserver to get access to Zynq
        • insert IP on web browser to start web interface
      • init.sh scripts
        • add init.sh script on SD, content will be load automatically on startup (template included in
      ./misc/SD
        • "<project folder>\misc\SD")

    Vivado Hardware Manager

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    Note:

    • Add picture of HW Manager

    • add notes for the signal either groups or topics, for example:

      Control:

      • add controllable IOs with short notes..

      Monitoring:

      • add short notes for signals which will be monitored only
      • SI5338
      _CLK0 Counter
      • CLKs:
       
        • Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
            • Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
            • expected CLK Frequency...
      Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
      • Control:
        • LEDs: XMOD 2 (without green dot) and HD LED are accessible.
        • CAN_S
      Scroll Title
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      titleVivado Hardware Manager



      System Design - Vivado

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      Note:

      • Description of Block Design, Constrains... BD Pictures from Export...

      Block Design


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      titleBlock Design


      PS Interfaces

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      Note:

      • optional for Zynq / ZynqMP only

      • add basic PS configuration
      Activated interfaces:


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      TypeNote
      DDR
      QSPIMIO
      SD0MIO
      SD1MIO
      CAN0EMIO
      I2C0MIO
      PJTAG0MIO
      UART0MIO
      GPIO0MIO
      SWDT0..1
      TTC0..3
      GEM3MIO
      USB0MIO/GTP
      PCIeMIO/GTP
      SATAGTPDisplayPort
      Display PortEMIO/GTP


      Constrains

      Basic module constrains

      Code Block
      languageruby
      title_i_bitgen.xdc
      set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
      set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

      Design specific constrain

      Code Block
      languageruby
      title_i_io.xdc
      #System Controller IP
        #LED_HD SC0 J3:31
        #LED_XMOD SC17 J3:48 
        #CAN RX SC19 J3:52 B47_L2_P in
        #CAN TX SC18 J3:50 B47_L2_N out 
        #CAN S  SC16 J3:46 B47_L3_N out
      set_property PACKAGE_PIN J14 [get_ports BASE_sc0]
      set_property PACKAGE_PIN G13 [get_ports BASE_sc5]
      set_property PACKAGE_PIN J15 [get_ports BASE_sc6]
      set_property PACKAGE_PIN K15 [get_ports BASE_sc7]
      set_property PACKAGE_PIN A15 [get_ports BASE_sc10_io]
      set_property PACKAGE_PIN B15 [get_ports BASE_sc11]
      set_property PACKAGE_PIN C13 [get_ports BASE_sc12]
      set_property PACKAGE_PIN C14 [get_ports BASE_sc13]
      set_property PACKAGE_PIN E13 [get_ports BASE_sc14]
      set_property PACKAGE_PIN E14 [get_ports BASE_sc15]
      set_property PACKAGE_PIN A13 [get_ports BASE_sc16]
      set_property PACKAGE_PIN B13 [get_ports BASE_sc17]
      set_property PACKAGE_PIN A14 [get_ports BASE_sc18]
      set_property PACKAGE_PIN B14 [get_ports BASE_sc19]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
      set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]
      
      # PLL
      #set_property PACKAGE_PIN AH6 [get_ports {si570_clk_p[0]}]
      #set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}]
      #set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}]
      # Clocks
      #set_property PACKAGE_PIN J8 [get_ports {B229_CLK1_clk_p[0]}]
      #set_property PACKAGE_PIN F25 [get_ports {B128_CLK0_clk_p[0]}]
      # SFP 
      #set_property PACKAGE_PIN G8 [get_ports {B230_CLK0_clk_p}]
      # B230_RX3_P
      #set_property PACKAGE_PIN A4 [get_ports {SFP1_rxp}]
      # B230_TX3_P
      #set_property PACKAGE_PIN A8 [get_ports {SFP1_txp}]
      # B230_RX2_P
      #set_property PACKAGE_PIN B2 [get_ports {SFP2_rxp}]
      # B230_TX2_P
      #set_property PACKAGE_PIN B6 [get_ports {SFP2_txp}]
      
      # Audio Codec
      #LRCLK          J3:49 B47_L9_N
      #BCLK            J3:51 B47_L9_P
      #DAC_SDATA    J3:53 B47_L7_N
      #ADC_SDATA    J3:55 B47_L7_P
      set_property PACKAGE_PIN G14 [get_ports LRCLK ]
      set_property PACKAGE_PIN G15 [get_ports BCLK ]
      set_property PACKAGE_PIN E15 [get_ports DAC_SDATA ]
      set_property PACKAGE_PIN F15 [get_ports ADC_SDATA ]
      set_property IOSTANDARD LVCMOS18 [get_ports LRCLK ]
      set_property IOSTANDARD LVCMOS18 [get_ports BCLK ]
      set_property IOSTANDARD LVCMOS18 [get_ports DAC_SDATA ]
      set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ]
      Software Design - Vitis
      ]

      Software Design - Vitis

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      Note:
      • optional chapter separate

      • sections for different apps

      For SDK Vitis project creation, follow instructions from:

      Vitis

      Application

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      ----------------------------------------------------------

      FPGA Example

      scu

      MCS Firmware to configure SI5338 and Reset System.

      srec_spi_bootloader

      TE modified 2020.2 SREC

      Bootloader to load app or second bootloader from flash into DDR

      Descriptions:

      • Modified Files: blconfig.h, bootloader.c
      • Changes:
        • Add some console outputs and changed bootloader read address.
        • Add bugfix for 2018.2 qspi flash

      xilisf_v5_11

      TE modified 2020.2 xilisf_v5_11

      • Changed default Flash type to 5.

      ----------------------------------------------------------

      Zynq Example:

      zynq_

      fsbl

      TE modified 2020.2 FSBL

      General:

      • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
      • Add Files: te_fsbl_hooks.h/.c (for hooks and board)\n\

      • General Changes: 
        • Display FSBL Banner and Device ID

      Module Specific:

      • Add Files: all TE Files start with te_*
        • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  uboot platform-top.h)
        • CPLD access
        • Read CPLD Firmware and SoC Type
        • Configure Marvell PHY
      zynq_

      fsbl_flash

      TE modified 2020.2 FSBL

      General:

      • Modified Files: main.c
      • General Changes:
        •  Display Display FSBL Banner
        • Set FSBL Boot Mode to JTAG
        • Disable Memory initialisation

      ZynqMP Example:

      ----------------------------------------------------------

      zynqmp_fsbl

      TE modified 2020.2 FSBL

      General:

      • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
      • Add Files:   te_xfsbl_hooks.h/.c (for hooks and board)\n\
      • General Changes: 
        • Display FSBL Banner and Device Name

      Module Specific:

      • Add Files: all TE Files start with te_*
        • Si5338 Configuration
        • ETH+OTG Reset over MIO

      zynqmp_fsbl_flash

      TE modified 2020.2 FSBL

      General:

      • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
      • General Changes:
        •  Display Display FSBL Banner
        • Set FSBL Boot Mode to JTAG
        • Disable Memory initialisation


      zynqmp_pmufw

      Xilinx default PMU firmware.

      ----------------------------------------------------------

      General Example:

      hello_te0820

      Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

      u-boot

      U-Boot.elf is generated with PetaLinux. SDK/HSI Vitis is used to generate Boot.bin.

      SDK template in ./Template location: "<project folder>\sw_lib/\sw_apps/ available.\"

      zynqmp_fsbl

      TE modified 2020.2 FSBL

      General:

      • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
      • Add Files:   te_xfsbl_hooks.h/.c (for hooks and board)\n\
      • General Changes: 
        • Display FSBL Banner and Device Name


      Module Specific:

      • Add Files: all TE Files start with te_*
        • Si5345 Configuration
        • OTG+PCIe Reset over MIO
        • I2C MUX for EEPROM MAC

      zynqmp_fsbl_flash

      TE modified 2020.2 FSBL

      General:

      • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
      • General Changes:
        •  Display Display FSBL Banner
        • Set FSBL Boot Mode to JTAG
        • Disable Memory initialisation

      zynqmp_pmufw

      Xilinx default PMU firmware.

      hello_te0808

      Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.

      u-boot

      U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

      Software Design -  PetaLinux

      .

      u-boot

      U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

      Software Design -  PetaLinux

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      Note:
      • optional chapter separate

      • sections for linux

      • Add "No changes." or "Activate: and add List"

      For PetaLinux installation and  and project creation, follow instructions from:

      Config

      Start with petalinux-config or petalinux-config --get-hw-description

      ActivateChanges:

      • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
      • CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""

      U-Boot

      Start with petalinux-config -c u-boot

      Changes:

      • CONFIG_I2C_EEPROM=y
      • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
      • CONFIG_SYS_I2C_EEPROM_ADDR=0x50
      • CONFIG_SYS_I2C_EEPROM_BUS=2
      • CONFIG_SYS_EEPROM_SIZE=256
      • CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
      • CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
      • CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
      • CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0
      • CONFIG_SD_BOOT=y

      Change platform-top.h:

      Code Block
      languagejs

      Device Tree

      Code Block
      languagejs
      /include/ "system-conf.dtsi"
      / {
        chosen {
          xlnx,eeprom = &eeprom;
        };
      };
      
      /* notes:
      serdes:
      https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/phy/phy-zynqmp.txt
      https://github.com/Xilinx/linux-xlnx/blob/master/include/dt-bindings/phy/phy.h
      */
      
      
      /* default */
      
      /* sata */
      
      &sata {
      phy-names = "sata-phy";
      phys = <&lane2 1  0 1 150000000>;
      };
      
      /* SD */
      &sdhci0 {
      	// disable-wp;
      	no-1-8-v;
      
      };
      
      &sdhci1 {
      	// disable-wp;
      	no-1-8-v;
      
      };
      
      
      /* USB  */
      
      
      &dwc3_0 {
          status = "okay";
          dr_mode = "host";
          snps,usb3_lpm_capable;
          snps,dis_u3_susphy_quirk;
          snps,dis_u2_susphy_quirk;
          phy-names = "usb2-phy","usb3-phy";
          phys = <&lane1 4 0 2 100000000>;
          maximum-speed = "super-speed";
      };
      
      /* ETH PHY */
      
      &gem3 {
      	phy-handle = <&phy0>;
      	phy0: phy0@1 {
      		device_type = "ethernet-phy";
      		reg = <1>;
      	};
      };
      
      /* QSPI */
      
      &qspi {
          #address-cells = <1>;
          #size-cells = <0>;
          status = "okay";
          flash0: flash@0 {
              compatible = "jedec,spi-nor";
              reg = <0x0>;
              #address-cells = <1>;
              #size-cells = <1>;
          };
      };
      
      /* I2C */
      
      &i2c0 {
          i2cswitch@73 { // u
              compatible = "nxp,pca9548";
              #address-cells = <1>;
              #size-cells = <0>;
              reg = <0x73>;
              i2c-mux-idle-disconnect;
              i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <0>;
              };
              i2c@1 { // SFP TEBF0808 PCF8574DWR
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <1>;
              };
              i2c@2 { // PCIe
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <2>;
              };
              i2c@3 { // SFP1 TEBF0808
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <3>;
              };
              i2c@4 {// SFP2 TEBF0808
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <4>;
              };
              i2c@5 { // TEBF0808 EEPROM
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <5>;
                  eeprom: eeprom@50 {
      	            compatible = "atmel,24c08";
      	            reg = <0x50>;
      	          };
              };
              i2c@6 { // TEBF0808 FMC  
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <6>;
              };
              i2c@7 { // TEBF0808 USB HUB
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <7>;
              };
          };
          i2cswitch@77 { // u
              compatible = "nxp,pca9548";
              #address-cells = <1>;
              #size-cells = <0>;
              reg = <0x77>;
              i2c-mux-idle-disconnect;
              i2c@0 { // TEBF0808 PMOD P1
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <0>;
              };
              i2c@1 { // i2c Audio Codec
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <1>;
      			/*
                  adau1761: adau1761@38 {
                      compatible = "adi,adau1761";
                      reg = <0x38>;
                  };
      			*/
              };
              i2c@2 { // TEBF0808 Firefly A
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <2>;
              };
              i2c@3 { // TEBF0808 Firefly B
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <3>;
              };
              i2c@4 { //Module PLL Si5338 or SI5345
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <4>;
              };
              i2c@5 { //TEBF0808 CPLD
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <5>;
              };
              i2c@6 { //TEBF0808 Firefly PCF8574DWR
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <6>;
              };
              i2c@7 { // TEBF0808 PMOD P3
                  #address-cells = <1>;
                  #size-cells = <0>;
                  reg = <7>;
              };
          };
      };
      
      
      
      
      

      FSBL patch

      Must be add manually, see template

      Kernel

      Start with petalinux-config -c kernel

      Changes:

      • # CONFIG_CPU_IDLE is not set
      • # CONFIG_CPU_FREQ is not set
      • CONFIG_EDAC_CORTEX_ARM64=y
      • # CONFIG_CPU_IDLE is not set
      • # CONFIG_CPU_FREQ is not set
      • CONFIG_NVME_CORE=y
      • CONFIG_BLK_DEV_NVME=y
      • # CONFIG_NVME_MULTIPATH is not set
      • # CONFIG_NVME_TCP is not set
      • CONFIG_NVME_TARGET=y
      • # CONFIG_NVME_TARGET_LOOP is not set
      • # CONFIG_NVME_TARGET_FC is not set
      • # CONFIG_NVME_TARGET_TCP is not set
      • CONFIG_NVM=y
      • CONFIG_NVM_PBLK=y
      • CONFIG_NVM_PBLK_DEBUG=y
      • CONFIG_EDAC_CORTEX_ARM64=y
      • CONFIG_SATA_AHCI=y
      • CONFIG_SATA_MOBILE_LPM_POLICY=0


      Rootfs

      Start with petalinux-config -c rootfs

      Changes:

      • CONFIG_i2c-tools=y
      • CONFIG_busybox-httpd=y (for web server app)
      • CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)

      Applications

      See : "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

      startup

      Script App to load init.sh from SD Card if available.

      webfwu

      Webserver application accemble for Zynq access. Need busybox-httpd

      Additional Software

      Script App to load init.sh from SD Card if available.

      webfwu

      Webserver application suitable for Zynq access. Need busybox-httpd

      Additional Software

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      Note:
      • Add description for other Software, for example SI CLK Builder ...
      • SI5338 and SI5345 also Link to:

      SI5345

      File location <design name>"<project folder>/misc/Si5345/Si5345-*.slabtimeproj"

      General documentation how you work with these project will be available on Si5345

      Appx. A: Change History and Legal Notices

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      Document Change History

      To get content of older revision  got revision go to "Change History"   of this page and select older document revision number.

      Page properties
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      • Note this list must be only updated, if the document is online on public doc!
      • It's semi automatically, so do following
        • Add new row below first

        • Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

        • Metadata is only used of compatibility of older exports


      Scroll Title
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      titleDocument change history.

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      DateDocument Revision

      Authors

      Description

      Page info
      infoTypeModified date
      dateFormatyyyy-MM-dd
      typeFlat

      Page info
      infoTypeCurrent version
      prefixv.
      typeFlat

      Page info
      infoTypeModified by
      typeFlat

      • Document Style update
      2021-05-12v.44John Hartfiel
      • update board files
      • update design
      2021-02-505v.43John Hartfiel
      • 2020.2 release
      • document style update
      2020-11-06v.41John Hartfiel
      • typo bugfix  for programming part
      2020-09-29v.40John Hartfiel
      • new assembly variants
      2020-03-25v.37John Hartfiel
      • script update
      2020-02-25v.35John Hartfiel
      • Update requirement section
      2020-01-23v.34John Hartfiel
      • new assembly variants
      • Release 2019.2
      2019-08-09v.32John Hartfiel
      • new assembly variants
      • small FSBL update
      • minor document style update
      2019-05-07v.29John Hartfiel
      • Release 2018.3
      2018-08-09v.27John Hartfiel
      • Release 2018.2

      2018-05-25

      v.21John Hartfiel
      • Solved known issues

      2018-04-30

      v.19John Hartfiel
      • Update known issues

      2018-03-29

      v.18John Hartfiel
      • New assembly variant
      2018-02-08v.16John Hartfiel
      • Solved known issues
      2018-01-29v.10John Hartfiel
      • Update known issues
      2018-01-18v.8John Hartfiel
      • Update documentation only
      2018-01-17v.7John Hartfiel
      • Update design
      2018-01-15v.4John Hartfiel
      • Release 2017.4
      2017-12-20v.2John Hartfiel
      • Release 2017.2

      All

      Page info
      infoTypeModified users
      typeFlat



      Legal Notices

      Include Page
      IN:Legal Notices
      IN:Legal Notices



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